A High-performance Timing Analysis Tool for VLSI Systems
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
Linux generic dhcp snooping daemon using nflog and ebtables or nftables
[ACL 2025] Beyond Prompt Engineering: Robust Behavior Control in LLMs via Steering Target Atoms
VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes contro…
Kho tài liệu đi từ nền tảng Điện tử căn bản đến Thiết kế vi mạch số, tập trung vào Front-End (RTL/DV). Tích hợp kiến thức bổ trợ cho các hướng công việc khác thuộc chuyên ngành Điện Tử. Biên soạn bởi Minh Ú (Phùng Quang Minh).
A reusable OpenClaw agent squad for chip architecture, RTL, DV, STA, PD, DFT, analog, and layout collaboration.
SensorThings work at DataCove
This repository is about the main project of the course "VLSI System Design". This course is part of my undergraduate studies on University of Thessally - ECE Department located in Volos, Greece.
Silicon Highway Technologies Free STA, ASTA Timing Engine
This project focuses on the design, verification, and physical implementation (RTL to GDSII) of full adder circuits using two architectural approaches: flat and hierarchical design methodologies. The entire digital ASIC flow is executed using Synopsys EDA tools, targeting a 32nm CMOS technology node.
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