A lightweight, background daemon for macOS that fixes the `00:00` clock issue on Ajazz wireless mouse dock screens (e.g., AJ179 Apex, AJ199, AJ159).

Time over android debuging bridge

Temporal contracts and governed time based state logic for Riverbraid.

Automatically synchronizes the Windows system clock at startup.

DIG-SYSTEM: A high-performance VHDL DPLL for Xilinx FPGAs. Implements IDELAYE2 primitives with sigma-delta dithering for sub-tap resolution. Features adaptive damping, phase velocity tracking, and robust hysteresis locking. Optimized for precision clock and data alignment.