From da05bed32f07ea43818885522c1892058fb4c7c4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E6=9D=8E=E9=80=9A=E6=B4=B2?= Date: Thu, 4 Jun 2026 17:32:52 +0800 Subject: [PATCH 01/19] CMake: exposes pre-defined macros to `fastfetch.c` to avoid imcompatiblity with `libfastfetch` --- CMakeLists.txt | 46 +++++++++++++++++++++++----------------------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index c0211aeda7..2323569b3a 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1576,24 +1576,24 @@ endif() if(NOT "${CUSTOM_PCI_IDS_PATH}" STREQUAL "") message(STATUS "Custom file path of pci.ids: ${CUSTOM_PCI_IDS_PATH}") - target_compile_definitions(libfastfetch PRIVATE FF_CUSTOM_PCI_IDS_PATH=${CUSTOM_PCI_IDS_PATH}) + target_compile_definitions(libfastfetch PUBLIC FF_CUSTOM_PCI_IDS_PATH=${CUSTOM_PCI_IDS_PATH}) endif() if(NOT "${CUSTOM_AMDGPU_IDS_PATH}" STREQUAL "") message(STATUS "Custom file path of amdgpu.ids: ${CUSTOM_AMDGPU_IDS_PATH}") - target_compile_definitions(libfastfetch PRIVATE FF_CUSTOM_AMDGPU_IDS_PATH=${CUSTOM_AMDGPU_IDS_PATH}) + target_compile_definitions(libfastfetch PUBLIC FF_CUSTOM_AMDGPU_IDS_PATH=${CUSTOM_AMDGPU_IDS_PATH}) endif() if(NOT "${CUSTOM_OS_RELEASE_PATH}" STREQUAL "") message(STATUS "Custom file path of os_release: ${CUSTOM_OS_RELEASE_PATH}") - target_compile_definitions(libfastfetch PRIVATE FF_CUSTOM_OS_RELEASE_PATH=${CUSTOM_OS_RELEASE_PATH}) + target_compile_definitions(libfastfetch PUBLIC FF_CUSTOM_OS_RELEASE_PATH=${CUSTOM_OS_RELEASE_PATH}) endif() if(NOT "${CUSTOM_LSB_RELEASE_PATH}" STREQUAL "") message(STATUS "Custom file path of lsb_release: ${CUSTOM_LSB_RELEASE_PATH}") - target_compile_definitions(libfastfetch PRIVATE FF_CUSTOM_LSB_RELEASE_PATH=${CUSTOM_LSB_RELEASE_PATH}) + target_compile_definitions(libfastfetch PUBLIC FF_CUSTOM_LSB_RELEASE_PATH=${CUSTOM_LSB_RELEASE_PATH}) endif() if(NOT BINARY_LINK_TYPE STREQUAL "dlopen") message(STATUS "Enabling custom link type: ${BINARY_LINK_TYPE}") - target_compile_definitions(libfastfetch PRIVATE FF_DISABLE_DLOPEN=1) + target_compile_definitions(libfastfetch PUBLIC FF_DISABLE_DLOPEN=1) if(NOT WIN32) set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -Wl,--copy-dt-needed-entries") endif() @@ -1659,18 +1659,18 @@ function(ff_lib_enable VARNAME PKGCONFIG_NAMES CMAKE_NAME) # [CMAKE_TARGET_NAME] message(STATUS "Library: found ${VARNAME} by ${${VARNAME}_FOUND}") - target_compile_definitions(libfastfetch PRIVATE FF_HAVE_${VARNAME}=1) + target_compile_definitions(libfastfetch PUBLIC FF_HAVE_${VARNAME}=1) target_include_directories(libfastfetch PRIVATE ${${VARNAME}_INCLUDE_DIRS}) if(NOT BINARY_LINK_TYPE STREQUAL "dlopen") - target_link_directories(libfastfetch PUBLIC ${${VARNAME}_LIBRARY_DIRS}) + target_link_directories(libfastfetch PRIVATE ${${VARNAME}_LIBRARY_DIRS}) target_link_libraries(libfastfetch PRIVATE ${${VARNAME}_LIBRARIES}) endif() foreach(FLAG ${${VARNAME}_CFLAGS_OTHER}) if(FLAG MATCHES "-D.*") string(SUBSTRING ${FLAG} 2 -1 FLAG) - target_compile_definitions(libfastfetch PRIVATE ${FLAG}) + target_compile_definitions(libfastfetch PUBLIC ${FLAG}) endif() endforeach() endfunction() @@ -1800,8 +1800,8 @@ if(ENABLE_LUA) message(STATUS "Library: Lua version ${Lua_VERSION} is not supported, requires 5.3-5.5") unset(Lua_FOUND) else() - target_compile_definitions(libfastfetch PRIVATE FF_HAVE_LUA=1) - target_include_directories(libfastfetch PRIVATE ${LUA_INCLUDE_DIR}) + target_compile_definitions(libfastfetch PUBLIC FF_HAVE_LUA=1) + target_include_directories(libfastfetch PUBLIC ${LUA_INCLUDE_DIR}) if(NOT BINARY_LINK_TYPE STREQUAL "dlopen") target_link_libraries(libfastfetch PRIVATE ${LUA_LIBRARIES}) @@ -1814,20 +1814,20 @@ if(ENABLE_LUA) endif() if(ENABLE_THREADS) - target_compile_definitions(libfastfetch PRIVATE FF_HAVE_THREADS=1) + target_compile_definitions(libfastfetch PUBLIC FF_HAVE_THREADS=1) if(CMAKE_USE_PTHREADS_INIT) #Threads::Threads is not set for WIN32 target_link_libraries(libfastfetch PRIVATE Threads::Threads) endif() endif() if(ENABLE_EMBEDDED_PCIIDS) - target_compile_definitions(libfastfetch PRIVATE FF_HAVE_EMBEDDED_PCIIDS=1) + target_compile_definitions(libfastfetch PUBLIC FF_HAVE_EMBEDDED_PCIIDS=1) endif() if(ENABLE_EMBEDDED_AMDGPUIDS) - target_compile_definitions(libfastfetch PRIVATE FF_HAVE_EMBEDDED_AMDGPUIDS=1) + target_compile_definitions(libfastfetch PUBLIC FF_HAVE_EMBEDDED_AMDGPUIDS=1) endif() if(ENABLE_LIBZFS) - target_compile_definitions(libfastfetch PRIVATE FF_HAVE_LIBZFS=1) + target_compile_definitions(libfastfetch PUBLIC FF_HAVE_LIBZFS=1) if(NOT BINARY_LINK_TYPE STREQUAL "dlopen") target_link_libraries(libfastfetch @@ -1984,7 +1984,7 @@ target_link_libraries(libfastfetch PRIVATE ${CMAKE_DL_LIBS} ) -target_compile_options(libfastfetch PRIVATE +target_compile_options(libfastfetch PUBLIC $<$:-fno-exceptions -fno-rtti>) if(FreeBSD) @@ -1993,18 +1993,18 @@ endif() if(LINUX OR FreeBSD OR OpenBSD OR NetBSD) CHECK_INCLUDE_FILE("linux/videodev2.h" HAVE_LINUX_VIDEODEV2) if(HAVE_LINUX_VIDEODEV2) - target_compile_definitions(libfastfetch PRIVATE FF_HAVE_LINUX_VIDEODEV2=1) + target_compile_definitions(libfastfetch PUBLIC FF_HAVE_LINUX_VIDEODEV2=1) endif() endif() if(NOT WIN32) CHECK_INCLUDE_FILE("utmpx.h" HAVE_UTMPX) if(HAVE_UTMPX) - target_compile_definitions(libfastfetch PRIVATE FF_HAVE_UTMPX=1) + target_compile_definitions(libfastfetch PUBLIC FF_HAVE_UTMPX=1) endif() if(ENABLE_WORDEXP) CHECK_INCLUDE_FILE("wordexp.h" HAVE_WORDEXP) if(HAVE_WORDEXP) - target_compile_definitions(libfastfetch PRIVATE FF_HAVE_WORDEXP=1) + target_compile_definitions(libfastfetch PUBLIC FF_HAVE_WORDEXP=1) message(STATUS "wordexp.h found, wordexp support enabled") else() set(ENABLE_WORDEXP OFF) @@ -2016,19 +2016,19 @@ if(NOT WIN32) if(ENABLE_THREADS AND CMAKE_USE_PTHREADS_INIT) CHECK_INCLUDE_FILE("pthread_np.h" HAVE_PTHREAD_NP) if(HAVE_PTHREAD_NP) - target_compile_definitions(libfastfetch PRIVATE FF_HAVE_PTHREAD_NP=1) + target_compile_definitions(libfastfetch PUBLIC FF_HAVE_PTHREAD_NP=1) set(CMAKE_REQUIRED_INCLUDES ${CMAKE_REQUIRED_INCLUDES} pthread_np.h) endif() set(CMAKE_REQUIRED_LIBRARIES ${CMAKE_REQUIRED_LIBRARIES} Threads::Threads) check_function_exists("pthread_timedjoin_np" HAVE_TIMEDJOIN_NP) if(HAVE_TIMEDJOIN_NP) - target_compile_definitions(libfastfetch PRIVATE FF_HAVE_TIMEDJOIN_NP=1) + target_compile_definitions(libfastfetch PUBLIC FF_HAVE_TIMEDJOIN_NP=1) else() message(WARNING "pthread_timedjoin_np was not found; networking timeout will not work") endif() endif() elseif(HAVE_WINRT) - target_compile_definitions(libfastfetch PRIVATE FF_HAVE_WINRT=1) + target_compile_definitions(libfastfetch PUBLIC FF_HAVE_WINRT=1) endif() set(PACKAGES_DISABLE_LIST "") @@ -2045,9 +2045,9 @@ else() list(TRANSFORM PACKAGES_DISABLE_LIST APPEND "_BIT") list(JOIN PACKAGES_DISABLE_LIST " | " PACKAGES_DISABLE_LIST) endif() -target_compile_definitions(libfastfetch PRIVATE "FF_PACKAGES_DISABLE_LIST=${PACKAGES_DISABLE_LIST}") +target_compile_definitions(libfastfetch PUBLIC "FF_PACKAGES_DISABLE_LIST=${PACKAGES_DISABLE_LIST}") if(PACKAGES_REMOVE_DISABLED) - target_compile_definitions(libfastfetch PRIVATE FF_PACKAGES_REMOVE_DISABLED=1) + target_compile_definitions(libfastfetch PUBLIC FF_PACKAGES_REMOVE_DISABLED=1) endif() ###################### From 135547fd50351d413c611b0b0a2a31dfe2c1f198 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E6=9D=8E=E9=80=9A=E6=B4=B2?= Date: Thu, 4 Jun 2026 18:27:36 +0800 Subject: [PATCH 02/19] Logo: don't accept chafa options when chafa is disabled --- src/logo/image/image.c | 32 +++++++++++++------------------- src/options/logo.c | 10 ++++++++++ src/options/logo.h | 2 ++ 3 files changed, 25 insertions(+), 19 deletions(-) diff --git a/src/logo/image/image.c b/src/logo/image/image.c index 78083e68e8..6dd3212151 100644 --- a/src/logo/image/image.c +++ b/src/logo/image/image.c @@ -727,7 +727,7 @@ FFLogoImageResult ffLogoPrintImageImpl(FFLogoRequestData* requestData, const FFI bool printSuccessful = false; if (requestData->type == FF_LOGO_TYPE_IMAGE_CHAFA) { - #ifdef FF_HAVE_CHAFA + #if FF_HAVE_CHAFA printSuccessful = printImageChafa(requestData, &imageData); #endif } else if (requestData->type == FF_LOGO_TYPE_IMAGE_KITTY) { @@ -782,12 +782,9 @@ static uint32_t readCachedUint32(FFLogoRequestData* requestData, const char* cac return result; } -static bool printCachedChars(FFLogoRequestData* requestData) { - FF_STRBUF_AUTO_DESTROY content = ffStrbufCreateA(32768); - - if (requestData->type == FF_LOGO_TYPE_IMAGE_CHAFA) { - readCachedStrbuf(requestData, &content, FF_CACHE_FILE_CHAFA); - } +static bool printCachedChars(FFLogoRequestData* requestData, const char* cacheFileName) { + FF_STRBUF_AUTO_DESTROY content = ffStrbufCreate(); + readCachedStrbuf(requestData, &content, cacheFileName); if (content.length == 0) { return false; @@ -876,14 +873,6 @@ static bool printCachedPixel(FFLogoRequestData* requestData) { return true; } -static bool printCached(FFLogoRequestData* requestData) { - if (requestData->type == FF_LOGO_TYPE_IMAGE_CHAFA) { - return printCachedChars(requestData); - } else { - return printCachedPixel(requestData); - } -} - static bool getCharacterPixelDimensions(FFLogoRequestData* requestData) { #ifdef _WIN32 @@ -947,9 +936,14 @@ static bool printImageIfExistsSlowPath(FFLogoType type, bool printError) { ffStrbufEnsureEndsWithC(&requestData.cacheDir, '/'); ffStrbufAppendF(&requestData.cacheDir, "%u*%u/", requestData.logoPixelWidth, requestData.logoPixelHeight); - if (!instance.config.logo.recache && printCached(&requestData)) { - ffStrbufDestroy(&requestData.cacheDir); - return true; + if (!instance.config.logo.recache) { + bool cacheValid = requestData.type == FF_LOGO_TYPE_IMAGE_CHAFA + ? printCachedChars(&requestData, FF_CACHE_FILE_CHAFA) + : printCachedPixel(&requestData); + if (cacheValid) { + ffStrbufDestroy(&requestData.cacheDir); + return true; + } } FFLogoImageResult result = FF_LOGO_IMAGE_RESULT_INIT_ERROR; @@ -1018,7 +1012,7 @@ bool ffLogoPrintImageIfExists(FFLogoType type, bool printError) { return printImageKittyIcat(printError); } -#if !defined(FF_HAVE_CHAFA) +#if !FF_HAVE_CHAFA if (type == FF_LOGO_TYPE_IMAGE_CHAFA) { if (printError) { fputs("Logo: Chafa support is not compiled in\n", stderr); diff --git a/src/options/logo.c b/src/options/logo.c index 6205b8ea8c..30fbccd4a1 100644 --- a/src/options/logo.c +++ b/src/options/logo.c @@ -20,11 +20,13 @@ void ffOptionsInitLogo(FFOptionsLogo* options) { options->recache = false; options->position = FF_LOGO_POSITION_LEFT; +#if FF_HAVE_CHAFA options->chafaFgOnly = false; ffStrbufInitStatic(&options->chafaSymbols, "block+border+space-wide-inverted"); // Chafa default options->chafaCanvasMode = UINT32_MAX; options->chafaColorSpace = UINT32_MAX; options->chafaDitherMode = UINT32_MAX; +#endif } bool ffOptionsParseLogoCommandLine(FFOptionsLogo* options, const char* key, const char* value) { @@ -160,6 +162,7 @@ bool ffOptionsParseLogoCommandLine(FFOptionsLogo* options, const char* key, cons if (subKey[0] == '\0') { ffOptionParseString(key, value, &options->source); options->type = FF_LOGO_TYPE_IMAGE_CHAFA; +#if FF_HAVE_CHAFA } else if (ffStrEqualsIgnCase(subKey, "fg-only")) { options->chafaFgOnly = ffOptionParseBoolean(value); } else if (ffStrEqualsIgnCase(subKey, "symbols")) { @@ -189,6 +192,7 @@ bool ffOptionsParseLogoCommandLine(FFOptionsLogo* options, const char* key, cons { "DIFFUSION", 2 }, {}, }); +#endif } else { return false; } @@ -201,7 +205,9 @@ bool ffOptionsParseLogoCommandLine(FFOptionsLogo* options, const char* key, cons void ffOptionsDestroyLogo(FFOptionsLogo* options) { ffStrbufDestroy(&options->source); +#if FF_HAVE_CHAFA ffStrbufDestroy(&options->chafaSymbols); +#endif for (uint8_t i = 0; i < (uint8_t) FASTFETCH_LOGO_MAX_COLORS; ++i) { ffStrbufDestroy(&options->colors[i]); } @@ -342,6 +348,7 @@ const char* ffOptionsParseLogoJsonConfig(FFOptionsLogo* options, yyjson_val* roo } options->position = (FFLogoPosition) value; continue; +#if FF_HAVE_CHAFA } else if (unsafe_yyjson_equals_str(key, "chafa")) { if (!yyjson_is_obj(val)) { return "Chafa config must be an object"; @@ -409,6 +416,7 @@ const char* ffOptionsParseLogoJsonConfig(FFOptionsLogo* options, yyjson_val* roo options->chafaDitherMode = (uint32_t) value; } continue; +#endif } else { return "Unknown logo key"; } @@ -515,6 +523,7 @@ void ffOptionsGenerateLogoJsonConfig(FFdata* data, FFOptionsLogo* options) { "right", })[options->position]); +#if FF_HAVE_CHAFA { yyjson_mut_val* chafa = yyjson_mut_obj(doc); yyjson_mut_obj_add_bool(doc, chafa, "fgOnly", options->chafaFgOnly); @@ -547,6 +556,7 @@ void ffOptionsGenerateLogoJsonConfig(FFdata* data, FFOptionsLogo* options) { yyjson_mut_obj_add_val(doc, obj, "chafa", chafa); } +#endif yyjson_mut_obj_add_val(doc, doc->root, "logo", obj); } diff --git a/src/options/logo.h b/src/options/logo.h index 21b63fff77..c77c678602 100644 --- a/src/options/logo.h +++ b/src/options/logo.h @@ -45,11 +45,13 @@ typedef struct FFOptionsLogo { bool preserveAspectRatio; bool recache; +#if FF_HAVE_CHAFA bool chafaFgOnly; FFstrbuf chafaSymbols; uint32_t chafaCanvasMode; uint32_t chafaColorSpace; uint32_t chafaDitherMode; +#endif } FFOptionsLogo; void ffOptionsInitLogo(FFOptionsLogo* options); From e24e3b6b29bb57ee34f6c8e99757a98fc2b36417 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E6=9D=8E=E9=80=9A=E6=B4=B2?= Date: Fri, 5 Jun 2026 22:18:53 +0800 Subject: [PATCH 03/19] Global: returns false when an error is printed --- src/modules/bluetooth/bluetooth.c | 1 + src/modules/bluetoothradio/bluetoothradio.c | 1 + src/modules/gpu/gpu.c | 19 ++++++++++--------- 3 files changed, 12 insertions(+), 9 deletions(-) diff --git a/src/modules/bluetooth/bluetooth.c b/src/modules/bluetooth/bluetooth.c index 641acebdc6..6721c336da 100644 --- a/src/modules/bluetooth/bluetooth.c +++ b/src/modules/bluetooth/bluetooth.c @@ -66,6 +66,7 @@ bool ffPrintBluetooth(FFBluetoothOptions* options) { if (devices.length == 0) { ffPrintError(FF_BLUETOOTH_MODULE_NAME, 0, &options->moduleArgs, FF_PRINT_TYPE_DEFAULT, "No bluetooth devices found"); + return false; } uint8_t i = 1; diff --git a/src/modules/bluetoothradio/bluetoothradio.c b/src/modules/bluetoothradio/bluetoothradio.c index 713931ab9e..594b00c298 100644 --- a/src/modules/bluetoothradio/bluetoothradio.c +++ b/src/modules/bluetoothradio/bluetoothradio.c @@ -113,6 +113,7 @@ bool ffPrintBluetoothRadio(FFBluetoothRadioOptions* options) { } else { ffPrintError(FF_BLUETOOTHRADIO_DISPLAY_NAME, 0, &options->moduleArgs, FF_PRINT_TYPE_DEFAULT, "No devices detected"); } + return false; } FF_LIST_FOR_EACH (FFBluetoothRadioResult, radio, radios) { diff --git a/src/modules/gpu/gpu.c b/src/modules/gpu/gpu.c index b0ace20006..5be84426e2 100644 --- a/src/modules/gpu/gpu.c +++ b/src/modules/gpu/gpu.c @@ -196,10 +196,6 @@ bool ffPrintGPU(FFGPUOptions* options) { ++i; } - if (selectedGPUs.length == 0) { - ffPrintError(FF_GPU_MODULE_NAME, 0, &options->moduleArgs, FF_PRINT_TYPE_DEFAULT, "No GPUs found"); - } - FF_LIST_FOR_EACH (FFGPUResult, gpu, gpus) { ffStrbufDestroy(&gpu->vendor); ffStrbufDestroy(&gpu->name); @@ -208,6 +204,11 @@ bool ffPrintGPU(FFGPUOptions* options) { ffStrbufDestroy(&gpu->memoryType); } + if (selectedGPUs.length == 0) { + ffPrintError(FF_GPU_MODULE_NAME, 0, &options->moduleArgs, FF_PRINT_TYPE_DEFAULT, (gpus.length > 0 ? "GPUs found but all hidden by hideType option" : "No GPUs detected")); + return false; + } + return true; } @@ -230,7 +231,7 @@ void ffParseGPUJsonObject(FFGPUOptions* options, yyjson_val* module) { if (unsafe_yyjson_equals_str(key, "detectionMethod")) { int value; - const char* error = ffJsonConfigParseEnum(val, &value, (FFKeyValuePair[]) { + const char* error = ffJsonConfigParseEnum(val, &value, (FFKeyValuePair[]){ { "auto", FF_GPU_DETECTION_METHOD_AUTO }, { "pci", FF_GPU_DETECTION_METHOD_PCI }, { "vulkan", FF_GPU_DETECTION_METHOD_VULKAN }, @@ -251,7 +252,7 @@ void ffParseGPUJsonObject(FFGPUOptions* options, yyjson_val* module) { options->hideType = FF_GPU_TYPE_NONE; } else { int value; - const char* error = ffJsonConfigParseEnum(val, &value, (FFKeyValuePair[]) { + const char* error = ffJsonConfigParseEnum(val, &value, (FFKeyValuePair[]){ { "none", FF_GPU_TYPE_NONE }, { "unknown", FF_GPU_TYPE_UNKNOWN }, { "integrated", FF_GPU_TYPE_INTEGRATED }, @@ -445,8 +446,8 @@ void ffInitGPUOptions(FFGPUOptions* options) { ; options->temp = false; options->hideType = FF_GPU_TYPE_NONE; - options->tempConfig = (FFColorRangeConfig) { 60, 80 }; - options->percent = (FFPercentageModuleConfig) { 50, 80, 0 }; + options->tempConfig = (FFColorRangeConfig){ 60, 80 }; + options->percent = (FFPercentageModuleConfig){ 50, 80, 0 }; } void ffDestroyGPUOptions(FFGPUOptions* options) { @@ -462,7 +463,7 @@ FFModuleBaseInfo ffGPUModuleInfo = { .printModule = (void*) ffPrintGPU, .generateJsonResult = (void*) ffGenerateGPUJsonResult, .generateJsonConfig = (void*) ffGenerateGPUJsonConfig, - .formatArgs = FF_FORMAT_ARG_LIST(((FFModuleFormatArg[]) { + .formatArgs = FF_FORMAT_ARG_LIST(((FFModuleFormatArg[]){ { "GPU vendor", "vendor" }, { "GPU name", "name" }, { "GPU driver", "driver" }, From c70620128203c3d707ce30bbe164e3621f4ca1aa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E6=9D=8E=E9=80=9A=E6=B4=B2?= Date: Sat, 6 Jun 2026 22:52:55 +0800 Subject: [PATCH 04/19] Global: adds some `always_inline` --- src/common/io.h | 42 ++++++++++++++++----------------------- src/common/mallocHelper.h | 2 ++ src/common/strutil.h | 11 ++++++++++ 3 files changed, 30 insertions(+), 25 deletions(-) diff --git a/src/common/io.h b/src/common/io.h index f7aec0b42f..e317120616 100644 --- a/src/common/io.h +++ b/src/common/io.h @@ -40,6 +40,7 @@ HANDLE openat(HANDLE dfd, const char* fileName, int oflag); HANDLE openatW(HANDLE dfd, const wchar_t* fileName, uint16_t fileNameLen, bool directory); #endif +FF_A_ALWAYS_INLINE static inline bool ffIsValidNativeFD(FFNativeFD fd) { #ifndef _WIN32 return fd >= 0; @@ -49,20 +50,17 @@ static inline bool ffIsValidNativeFD(FFNativeFD fd) { #endif } -FF_A_NONNULL(1) static inline bool wrapClose(FFNativeFD* pfd) { +FF_A_ALWAYS_INLINE FF_A_NONNULL(1) +static inline void wrapClose(FFNativeFD* pfd) { assert(pfd); - if (!ffIsValidNativeFD(*pfd)) { - return false; - } - + if (ffIsValidNativeFD(*pfd)) { #ifndef _WIN32 - close(*pfd); + close(*pfd); #else - NtClose(*pfd); + NtClose(*pfd); #endif - - return true; + } } #define FF_AUTO_CLOSE_FD FF_A_CLEANUP(wrapClose) @@ -250,34 +248,28 @@ static inline void ffUnsuppressIO(bool* suppressed) { void ffListFilesRecursively(const char* path, bool pretty); -FF_A_NONNULL(1) static inline bool wrapFclose(FILE** pfile) { +FF_A_NONNULL(1) FF_A_ALWAYS_INLINE static inline void wrapFclose(FILE** pfile) { assert(pfile); - if (!*pfile) { - return false; + if (*pfile) { + fclose(*pfile); } - fclose(*pfile); - return true; } #define FF_AUTO_CLOSE_FILE FF_A_CLEANUP(wrapFclose) -FF_A_NONNULL(1) +FF_A_NONNULL(1) FF_A_ALWAYS_INLINE #ifndef _WIN32 -static inline bool wrapClosedir(DIR** pdir) { +static inline void wrapClosedir(DIR** pdir) { assert(pdir); - if (!*pdir) { - return false; + if (*pdir) { + closedir(*pdir); } - closedir(*pdir); - return true; } #else -static inline bool wrapClosedir(HANDLE* pdir) { +static inline void wrapClosedir(HANDLE* pdir) { assert(pdir); - if (!*pdir) { - return false; + if (*pdir) { + FindClose(*pdir); } - FindClose(*pdir); - return true; } #endif #define FF_AUTO_CLOSE_DIR FF_A_CLEANUP(wrapClosedir) diff --git a/src/common/mallocHelper.h b/src/common/mallocHelper.h index 5b24df4713..a130118388 100644 --- a/src/common/mallocHelper.h +++ b/src/common/mallocHelper.h @@ -2,6 +2,7 @@ #include #include +#include "common/attributes.h" #if FF_HAVE_MALLOC_USABLE_SIZE || FF_HAVE_MSVC_MSIZE #if __has_include() @@ -13,6 +14,7 @@ #include #endif +FF_A_ALWAYS_INLINE FF_A_NONNULL(1) static inline void ffWrapFree(const void* pPtr) { assert(pPtr); if (*(void**) pPtr) { diff --git a/src/common/strutil.h b/src/common/strutil.h index 00a8a08398..f21528fb57 100644 --- a/src/common/strutil.h +++ b/src/common/strutil.h @@ -5,6 +5,7 @@ #include #include +#include "common/attributes.h" #include "common/wcwidth.h" #ifdef _WIN32 @@ -25,14 +26,17 @@ static inline bool ffStrSet(const char* str) { return *str != '\0'; } +FF_A_ALWAYS_INLINE static inline bool ffStrStartsWithIgnCase(const char* str, const char* compareTo) { return strncasecmp(str, compareTo, strlen(compareTo)) == 0; } +FF_A_ALWAYS_INLINE static inline bool ffStrEqualsIgnCase(const char* str, const char* compareTo) { return strcasecmp(str, compareTo) == 0; } +FF_A_ALWAYS_INLINE static inline bool ffStrStartsWith(const char* str, const char* compareTo) { return strncmp(str, compareTo, strlen(compareTo)) == 0; } @@ -55,26 +59,32 @@ static inline bool ffStrEndsWithIgnCase(const char* str, const char* compareTo) return strncasecmp(str + strLength - compareToLength, compareTo, compareToLength) == 0; } +FF_A_ALWAYS_INLINE static inline bool ffStrEquals(const char* str, const char* compareTo) { return strcmp(str, compareTo) == 0; } +FF_A_ALWAYS_INLINE static inline bool ffStrContains(const char* str, const char* compareTo) { return strstr(str, compareTo) != NULL; } +FF_A_ALWAYS_INLINE static inline bool ffStrContainsIgnCase(const char* str, const char* compareTo) { return strcasestr(str, compareTo) != NULL; } +FF_A_ALWAYS_INLINE static inline bool ffStrContainsC(const char* str, char compareTo) { return strchr(str, compareTo) != NULL; } +FF_A_ALWAYS_INLINE static inline bool ffCharIsEnglishAlphabet(char c) { return ('a' <= c && c <= 'z') || ('A' <= c && c <= 'Z'); } +FF_A_ALWAYS_INLINE static inline bool ffCharIsDigit(char c) { return '0' <= c && c <= '9'; } @@ -86,6 +96,7 @@ uint8_t ffUtf8CharLenWidth(const char* str, uint32_t length, uint8_t* width); uint32_t ffUtf8StrWidth(const char* str, uint32_t length); +FF_A_ALWAYS_INLINE static inline bool ffCharIsHexDigit(char c) { return ffCharIsDigit(c) || ('a' <= c && c <= 'f') || ('A' <= c && c <= 'F'); } From e936ddef6b58cc1876f9e08ed5e26689a440b848 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E6=9D=8E=E9=80=9A=E6=B4=B2?= Date: Sun, 7 Jun 2026 10:46:37 +0800 Subject: [PATCH 05/19] CPU (X86): adds code name and tech detection Fixes #1501 --- CMakeLists.txt | 1 + src/detection/cpu/cpu.c | 5 + src/detection/cpu/cpu.h | 11 + src/detection/cpu/cpu_x86.c | 1400 +++++++++++++++++++++++++++++++++++ src/modules/cpu/cpu.c | 22 + 5 files changed, 1439 insertions(+) create mode 100644 src/detection/cpu/cpu_x86.c diff --git a/CMakeLists.txt b/CMakeLists.txt index 2323569b3a..fdb746e295 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -447,6 +447,7 @@ set(LIBFASTFETCH_SRC src/detection/codec/codec.c src/detection/codec/codec_vulkan.c src/detection/cpu/cpu.c + src/detection/cpu/cpu_x86.c src/detection/cpuusage/cpuusage.c src/detection/command/command.c src/detection/disk/disk.c diff --git a/src/detection/cpu/cpu.c b/src/detection/cpu/cpu.c index aadcdc452d..155c0328c8 100644 --- a/src/detection/cpu/cpu.c +++ b/src/detection/cpu/cpu.c @@ -22,6 +22,11 @@ const char* ffDetectCPU(const FFCPUOptions* options, FFCPUResult* cpu) { ffStrbufSubstrBeforeFirstC(&cpu->name, '@'); // Cut the speed output in the name as we append our own ffStrbufTrimRight(&cpu->name, ' '); // If we removed the @ in previous step there was most likely a space before it ffStrbufRemoveDupWhitespaces(&cpu->name); + +#if __i386__ || __x86_64__ + ffCPUDetectX86Specific(cpu); +#endif + return NULL; } diff --git a/src/detection/cpu/cpu.h b/src/detection/cpu/cpu.h index 0f7eeceb53..4e47ca10a6 100644 --- a/src/detection/cpu/cpu.h +++ b/src/detection/cpu/cpu.h @@ -27,9 +27,20 @@ typedef struct FFCPUResult { FFCPUCore coreTypes[16]; // number of P cores, E cores, etc. double temperature; + + #if __i386__ || __x86_64__ + const char* codeName; + const char* technology; + #endif } FFCPUResult; const char* ffDetectCPU(const FFCPUOptions* options, FFCPUResult* cpu); const char* ffCPUAppleCodeToName(uint32_t code); const char* ffCPUQualcommCodeToName(uint32_t code); void ffCPUDetectByCpuid(FFCPUResult* cpu); + +#if __i386__ || __x86_64__ + +bool ffCPUDetectX86Specific(FFCPUResult* cpu); + +#endif diff --git a/src/detection/cpu/cpu_x86.c b/src/detection/cpu/cpu_x86.c new file mode 100644 index 0000000000..b5e61e05b5 --- /dev/null +++ b/src/detection/cpu/cpu_x86.c @@ -0,0 +1,1400 @@ +#include "cpu.h" + +#if __x86_64__ || __i386__ + #include + #include "common/strutil.h" + + #define UNKN_STR "Unknown" + +typedef struct match_entry_t { + int32_t family, model, stepping, ext_family, ext_model; // -1 means wildcard + int32_t ncores, l2cache, l3cache; + struct { + const char* pattern; + int32_t score; + } brand; + const char* name; + const char* technology; +} FFCPUX86MatchEntry; + +/////////////////////////////////////////////////////////////////////////////////////////////// + +// clang-format off + +// From libcpuid: https://github.com/anrieff/libcpuid +// LICENSE: BSD-2-Clause + +/****************************************** Intel ****************************************** */ + +// https://github.com/anrieff/libcpuid/blob/2e4456ae0165db3155da2e8fba92afd5c090ca1b/libcpuid/recog_intel.c +/* + * Copyright 2008 Veselin Georgiev, + * anrieffNOSPAM @ mgail_DOT.com (convert to gmail) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Useful links: + * - List of Intel CPU microarchitectures: https://en.wikipedia.org/wiki/List_of_Intel_CPU_microarchitectures + * - List of Intel processors: https://en.wikipedia.org/wiki/List_of_Intel_processors + * - List of Intel Pentium processors: https://en.wikipedia.org/wiki/List_of_Intel_Pentium_processors + * - List of Intel Celeron processors: https://en.wikipedia.org/wiki/List_of_Intel_Celeron_processors + * - List of Intel Core processors: https://en.wikipedia.org/wiki/List_of_Intel_Core_processors + * - List of Intel Xeon processors: https://en.wikipedia.org/wiki/List_of_Intel_Xeon_processors +*/ +const struct match_entry_t cpudb_intel[] = { +// F M S EF EM #cores L2$ L3$ Pattern Codename Technology + { -1, -1, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown Intel CPU", UNKN_STR }, + + /* i486 */ + { 4, -1, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown i486", UNKN_STR }, + { 4, 0, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 DX-25/33", "1 µm" }, + { 4, 1, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 DX-50", "0.8 µm" }, + { 4, 2, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 SX", UNKN_STR }, + { 4, 3, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 DX2", UNKN_STR }, + { 4, 4, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 SL", "0.8 µm" }, + { 4, 5, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 SX2", UNKN_STR }, + { 4, 7, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 DX2 WriteBack", UNKN_STR }, + { 4, 8, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 DX4", "0.6 µm" }, + { 4, 9, -1, -1, -1, 1, -1, -1, { "", 0 }, "i486 DX4 WriteBack", "0.6 µm" }, + + /* P6 CPUs */ + { 5, 0, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium A-Step", UNKN_STR }, + { 5, 1, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 1", "0.8 µm" }, + { 5, 2, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 1", "0.35 µm" }, + { 5, 3, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium OverDrive", UNKN_STR }, + { 5, 4, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 1", "0.35 µm" }, + { 5, 7, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 1", "0.35 µm" }, + { 5, 8, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium MMX", "0.25 µm" }, + + /* P6 CPUs */ + { 6, 0, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium Pro", UNKN_STR }, + { 6, 1, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium Pro", UNKN_STR }, + { 6, 3, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium II (Klamath)", "0.18 µm" }, + { 6, 5, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium II (Deschutes)", "0.18 µm" }, + { 6, 5, -1, -1, -1, 1, -1, -1, { "Pentium(R) M", 4 }, "Mobile Pentium II (Tonga)", "0.18 µm" }, + { 6, 6, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium II (Dixon)", "0.25 µm" }, + { 6, 3, -1, -1, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "P-II Xeon (Klamath)", "0.35 µm" }, + { 6, 5, -1, -1, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "P-II Xeon (Drake)", "0.25 µm" }, + { 6, 6, -1, -1, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "P-II Xeon (Dixon)", "0.25 µm" }, + { 6, 5, -1, -1, -1, 1, -1, -1, { "Celeron(R)", 2 }, "P-II Celeron (Covington)", "0.25 µm" }, + { 6, 6, -1, -1, -1, 1, -1, -1, { "Celeron(R)", 2 }, "P-II Celeron (Mendocino)", "0.25 µm" }, + { 6, 7, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium III (Katmai)", "0.25 µm" }, + { 6, 8, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium III (Coppermine)", "0.18 µm" }, + { 6, 10, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium III (Coppermine)", "0.18 µm" }, + { 6, 11, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium III (Tualatin)", "0.13 µm" }, + { 6, 11, -1, -1, -1, 1, 512, -1, { "Pentium(R)", 2 }, "Pentium III (Tualatin)", "0.13 µm" }, + { 6, 7, -1, -1, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "P-III Xeon (Tanner)", "0.25 µm" }, + { 6, 8, -1, -1, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "P-III Xeon (Cascades)", "0.18 µm" }, + { 6, 10, -1, -1, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "P-III Xeon (Cascades)", "0.18 µm" }, + { 6, 11, -1, -1, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "P-III Xeon (Tualatin)", "0.13 µm" }, + { 6, 7, -1, -1, -1, 1, 128, -1, { "Celeron(R)", 2 }, "P-III Celeron (Katmai)", "0.25 µm" }, + { 6, 8, -1, -1, -1, 1, 128, -1, { "Celeron(R)", 2 }, "P-III Celeron (Coppermine)", "0.18 µm" }, + { 6, 10, -1, -1, -1, 1, 128, -1, { "Celeron(R)", 2 }, "P-III Celeron (Coppermine)", "0.18 µm" }, + { 6, 11, -1, -1, -1, 1, 256, -1, { "Celeron(R)", 2 }, "P-III Celeron (Tualatin)", "0.13 µm" }, + + /* NetBurst CPUs */ + /* Willamette (2000, 180 nm): */ + { 15, 0, -1, 15, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 4 (Willamette)", "0.18 µm" }, + { 15, 1, -1, 15, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 4 (Willamette)", "0.18 µm" }, + { 15, 0, -1, 15, -1, 1, -1, -1, { "Pentium(R) 4 - M", 6 }, "Mobile P-4 (Willamette)", "0.18 µm" }, + { 15, 1, -1, 15, -1, 1, -1, -1, { "Pentium(R) 4 - M", 6 }, "Mobile P-4 (Willamette)", "0.18 µm" }, + { 15, 1, -1, 15, -1, 1, -1, -1, { "Celeron(R)", 2 }, "P-4 Celeron (Willamette)", "0.18 µm" }, + { 15, 0, -1, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Foster)", "0.18 µm" }, + { 15, 1, -1, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Foster)", "0.18 µm" }, + /* Northwood / Mobile Pentium 4 / Banias (2002, 130 nm): */ + { 15, 2, -1, 15, -1, 1, -1, -1, { "Pentium(R) 4", 2 }, "Pentium 4 (Northwood)", "0.13 µm" }, + { 15, 2, -1, 15, -1, 1, -1, -1, { "Pentium(R) 4 - M", 6 }, "Mobile P-4 (Northwood)", "0.13 µm" }, + { 15, 2, -1, 15, -1, 1, -1, -1, { "Celeron(R)", 2 }, "P-4 Celeron (Northwood)", "0.13 µm" }, + { 6, 9, -1, -1, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium M (Banias)", "0.13 µm" }, + { 6, 9, -1, -1, -1, 1, -1, -1, { "Pentium(R) 4 - M", 6 }, "Pentium M (Banias)", "0.13 µm" }, + { 6, 9, -1, -1, -1, 1, -1, -1, { "Celeron(R)", 2 }, "Celeron M (Banias)", "0.13 µm" }, + { 6, 9, -1, -1, -1, 1, -1, -1, { "Celeron(R) M", 4 }, "Celeron M (Banias)", "0.13 µm" }, + { 6, 9, -1, -1, -1, 1, 0, -1, { "Celeron(R)", 2 }, "Celeron M (Shelton)", "0.13 µm" }, + { 15, 2, -1, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Prestonia)", "0.13 µm" }, + { 15, 2, -1, 15, -1, 1, -1, -1, { "Xeon(TM) MP", 4 }, "Xeon (Gallatin)", "0.13 µm" }, + /* Prescott / Dothan (2004, 90 nm): */ + { 15, 3, -1, 15, -1, 1, -1, -1, { "Pentium(R) 4", 4 }, "Pentium 4 (Prescott)", "90 nm" }, + { 15, 4, -1, 15, -1, 1, -1, -1, { "Pentium(R) 4", 4 }, "Pentium 4 (Prescott)", "90 nm" }, + { 15, 3, -1, 15, -1, 1, -1, -1, { "Pentium(R) 4 - M", 6 }, "Mobile P-4 (Prescott)", "90 nm" }, + { 15, 4, -1, 15, -1, 1, -1, -1, { "Pentium(R) 4 - M", 6 }, "Mobile P-4 (Prescott)", "90 nm" }, + { 15, 3, -1, 15, -1, 1, -1, -1, { "Celeron(R)", 2 }, "P-4 Celeron D (Prescott)", "90 nm" }, + { 15, 4, -1, 15, -1, 1, -1, -1, { "Celeron(R)", 2 }, "P-4 Celeron D (Prescott)", "90 nm" }, + { 15, 4, -1, 15, -1, 1, -1, -1, { "Pentium(R) D", 4 }, "Pentium D (SmithField)", "90 nm" }, + { 6, 13, -1, -1, -1, 1, -1, -1, { "Pentium(R) M", 4 }, "Pentium M (Dothan)", "90 nm" }, + { 6, 13, -1, -1, -1, 1, -1, -1, { "Pentium(R) 4 - M", 6 }, "Pentium M (Dothan)", "90 nm" }, + { 6, 13, -1, -1, -1, 1, -1, -1, { "Celeron(R)", 2 }, "Celeron M (Dothan)", "90 nm" }, + { 6, 13, -1, -1, -1, 1, -1, -1, { "Celeron(R) M", 4 }, "Celeron M (Dothan)", "90 nm" }, + { 15, 3, -1, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Nocona)", "90 nm" }, + { 15, 4, -1, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Nocona)", "90 nm" }, + { 15, 4, 3, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Irwindale)", "90 nm" }, + { 15, 4, 10, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Irwindale)", "90 nm" }, + { 15, 4, 1, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Cranford)", "90 nm" }, + { 15, 4, -1, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Potomac)", "90 nm" }, + { 15, 4, 8, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Paxville)", "90 nm" }, + /* Cedar Mill / Yonah / Presler (2006, 65 nm): */ + { 15, 6, -1, 15, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium 4 (Cedar Mill)", "65 nm" }, + { 15, 6, -1, 15, -1, 1, -1, -1, { "Pentium(R) 4 - M", 6 }, "Mobile P-4 (Cedar Mill)", "65 nm" }, + { 15, 6, -1, 15, -1, 1, -1, -1, { "Celeron(R) D", 4 }, "P-4 Celeron D (Cedar Mill)", "65 nm" }, + { 6, 14, -1, 14, -1, 1, -1, -1, { "Core(TM) [UT]1#[05]0", 6 }, "Core Solo (Yonah)", "65 nm" }, + { 6, 14, -1, 14, -1, 1, -1, -1, { "Core(TM) 1#[05]0", 4 }, "Core Solo (Yonah)", "65 nm" }, + { 6, 14, -1, 14, -1, 2, -1, -1, { "Core(TM) Duo [UTL]2#[05]#", 6 }, "Core Duo (Yonah)", "65 nm" }, + { 6, 14, -1, 14, -1, 2, -1, -1, { "Core(TM) Duo 2#[05]#", 4 }, "Core Duo (Yonah)", "65 nm" }, + { 6, 14, -1, 14, -1, -1, -1, -1, { "Celeron(R) 215", 6 }, "Celeron (Yonah-512)", "65 nm" }, + { 6, 14, -1, 14, -1, -1, -1, -1, { "Celeron(R) M", 4 }, "Celeron (Yonah-1024)", "65 nm" }, + { 15, 6, -1, 15, -1, 1, -1, -1, { "Pentium(R) D", 4 }, "Pentium D (Presler)", "65 nm" }, + { 15, 6, 2, 15, -1, 1, -1, -1, { "Pentium(R)", 2 }, "Pentium Extreme Edition (Presler)", "65 nm" }, + { 15, 6, 4, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Dempsey)", "65 nm" }, + { 15, 6, 6, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Tulsa)", "65 nm" }, + { 15, 6, 8, 15, -1, 1, -1, -1, { "Xeon(TM)", 2 }, "Xeon (Tulsa)", "65 nm" }, + + /* Core CPUs (2006, 65 nm): https://en.wikipedia.org/wiki/Intel_Core_(microarchitecture)*/ + { 6, 15, -1, -1, -1, 2, 2048, -1, { "Core(TM)2 Duo E6###", 8 }, "Core 2 Duo (Conroe-2M)", "65 nm" }, + { 6, 15, -1, -1, -1, 2, 4096, -1, { "Core(TM)2 Duo E6###", 8 }, "Core 2 Duo (Conroe)", "65 nm" }, + { 6, 15, -1, -1, -1, 2, 4096, -1, { "Core(TM)2 6###", 4 }, "Core 2 Duo (Conroe)", "65 nm" }, + { 6, 15, -1, -1, -1, 2, 4096, -1, { "Core(TM)2 X6###", 6 }, "Core 2 Extreme (Conroe XE)", "65 nm" }, + { 6, 15, -1, -1, -1, 4, 4096, -1, { "Core(TM)2 Quad Q6###", 8 }, "Core 2 Quad (Kentsfield)", "65 nm" }, + { 6, 15, -1, -1, -1, 2, 2048, -1, { "Core(TM)2 Duo E4###", 8 }, "Core 2 Duo (Allendale)", "65 nm" }, + { 6, 15, -1, -1, 15, 2, 2048, -1, { "Core(TM)2 U7###", 6 }, "Core 2 Duo (Merom-2M)", "65 nm" }, + { 6, 15, -1, -1, 15, 2, 2048, -1, { "Core(TM)2 T[57]###", 6 }, "Core 2 Duo (Merom-2M)", "65 nm" }, + { 6, 15, -1, -1, 15, 2, 4096, -1, { "Core(TM)2 T7###", 6 }, "Core 2 Duo (Merom)", "65 nm" }, + { 6, 15, -1, -1, 15, 2, 4096, -1, { "Core(TM)2 S[LP]7###", 6 }, "Core 2 Duo (Merom)", "65 nm" }, + { 6, 15, -1, -1, 15, 2, 4096, -1, { "Core(TM)2 L7###", 6 }, "Core 2 Duo (Merom)", "65 nm" }, + { 6, 15, -1, -1, 15, 2, -1, -1, { "Pentium(R) Dual E2###", 8 }, "Pentium Dual-Core (Allendale)", "65 nm" }, + { 6, 15, -1, -1, 15, 2, -1, -1, { "Celeron(R) E1###", 6 }, "Celeron (Allendale)", "65 nm" }, + { 6, 6, -1, -1, 22, 1, -1, -1, { "Celeron(R) [24]##", 4 }, "Celeron (Conroe-L)", "65 nm" }, + { 6, 14, -1, -1, 14, 1, -1, -1, { "Xeon(R) 51##", 4 }, "Xeon LV (Woodcrest)", "65 nm" }, + { 6, 15, -1, -1, 15, 2, -1, -1, { "Xeon(R) 51##", 4 }, "Xeon (Woodcrest)", "65 nm" }, + { 6, 15, -1, -1, 15, 2, -1, -1, { "Xeon(R) 30##", 4 }, "Xeon (Conroe)", "65 nm" }, + { 6, 15, -1, -1, 15, 4, -1, -1, { "Xeon(R) X32##", 6 }, "Xeon (Kentsfield)", "65 nm" }, + { 6, 15, -1, -1, 15, 4, -1, -1, { "Xeon(R) [EXL]53##", 6 }, "Xeon (Clovertown)", "65 nm" }, + + /* Penryn CPUs (2007, 45 nm): https://en.wikipedia.org/wiki/Penryn_(microarchitecture) */ + { 6, 7, -1, -1, 23, 2, 1024, -1, { "Celeron(R) E3###", 6 }, "Celeron (Wolfdale-3M)", "45 nm" }, + { 6, 7, -1, -1, 23, 2, 1024, -1, { "Pentium(R) E2###", 6 }, "Celeron (Wolfdale-3M)", "45 nm" }, + { 6, 7, -1, -1, 23, 2, 2048, -1, { "Pentium(R) E[56]###", 6 }, "Pentium (Wolfdale-3M)", "45 nm" }, + { 6, 7, -1, -1, 23, 2, 3072, -1, { "Core(TM)2 Duo E7###", 8 }, "Core 2 Duo (Wolfdale-3M)", "45 nm" }, + { 6, 7, -1, -1, 23, 2, 6144, -1, { "Core(TM)2 Duo E8###", 8 }, "Core 2 Duo (Wolfdale)", "45 nm" }, + { 6, 7, -1, -1, 23, 2, 1024, -1, { "Pentium(R) Dual-Core T4###", 8 }, "Pentium Dual-Core (Penryn-L)", "45 nm" }, + { 6, 7, -1, -1, 23, 1, 1024, -1, { "Celeron(R) [79]##", 4 }, "Celeron (Penryn-L)", "45 nm" }, + { 6, 7, -1, -1, 23, 2, 3072, -1, { "Core(TM)2 Duo SU[78]###", 8 }, "Core 2 Duo (Penryn-3M)", "45 nm" }, + { 6, 7, -1, -1, 23, 2, 3072, -1, { "Core(TM)2 Duo P[78]###", 8 }, "Core 2 Duo (Penryn-3M)", "45 nm" }, + { 6, 7, -1, -1, 23, 2, 2048, -1, { "Core(TM)2 Duo T6###", 8 }, "Core 2 Duo (Penryn-3M)", "45 nm" }, + { 6, 7, -1, -1, 23, 2, 3072, -1, { "Core(TM)2 Duo T8###", 8 }, "Core 2 Duo (Penryn-3M)", "45 nm" }, + { 6, 7, -1, -1, 23, 2, 6144, -1, { "Core(TM)2 Duo S[LP]9###", 8 }, "Core 2 Duo (Penryn)", "45 nm" }, + { 6, 7, -1, -1, 23, 2, 6144, -1, { "Core(TM)2 Duo [PT]9###", 8 }, "Core 2 Duo (Penryn)", "45 nm" }, + { 6, 7, -1, -1, 23, 2, 6144, -1, { "Core(TM)2 Duo E8###", 8 }, "Core 2 Duo (Penryn)", "45 nm" }, + { 6, 7, -1, -1, 23, 4, 2048, -1, { "Core(TM)2 Quad Q8###", 8 }, "Core 2 Quad (Yorkfield-6M)", "45 nm" }, /* 2×2 MB L2$ */ + { 6, 7, -1, -1, 23, 4, 3072, -1, { "Core(TM)2 Quad Q9#0#", 8 }, "Core 2 Quad (Yorkfield-6M)", "45 nm" }, /* 2×3 MB L2$ */ + { 6, 7, -1, -1, 23, 4, 6144, -1, { "Core(TM)2 Quad Q9#5#", 8 }, "Core 2 Quad (Yorkfield)", "45 nm" }, /* 2×6 MB L2$ */ + { 6, 7, -1, -1, 23, 2, -1, -1, { "Xeon(R) [EL]31##", 6 }, "Xeon (Wolfdale)", "45 nm" }, + { 6, 7, -1, -1, 23, 2, -1, -1, { "Xeon(R) [EXL]52##", 6 }, "Xeon (Wolfdale DP)", "45 nm" }, + { 6, 7, -1, -1, 23, 4, -1, -1, { "Xeon(R) [EXL]54##", 6 }, "Xeon (Harpertown)", "45 nm" }, + { 6, 7, -1, -1, 23, 4, -1, -1, { "Xeon(R) [XL]33##", 6 }, "Xeon (Yorkfield)" , "45 nm" }, + { 6, 13, -1, -1, 29, -1, -1, -1, { "Xeon(R) [EXL]74##", 6 }, "Xeon (Dunnington)", "45 nm" }, + + /* Nehalem CPUs (2008, 1st Core i gen, 45 nm): https://en.wikipedia.org/wiki/Nehalem_(microarchitecture) */ + { 6, 10, -1, -1, 26, -1, -1, -1, { "Xeon(R) [WELX]5###", 6 }, "Xeon (Gainestown)", "45 nm" }, + { 6, 10, -1, -1, 26, -1, -1, -1, { "Xeon(R) [WELX]3###", 6 }, "Xeon (Bloomfield)", "45 nm" }, + { 6, 10, -1, -1, 26, -1, -1, -1, { "Core(TM) i7 9#5", 8 }, "Core i7 Extreme (Bloomfield)", "45 nm" }, + { 6, 10, -1, -1, 26, -1, -1, -1, { "Core(TM) i7 9#0", 8 }, "Core i7 (Bloomfield)", "45 nm" }, + { 6, 14, -1, -1, 30, -1, -1, -1, { "Core(TM) i7 8##", 8 }, "Core i7 (Lynnfield)", "45 nm" }, + { 6, 14, -1, -1, 30, -1, -1, -1, { "Core(TM) i5 7##", 8 }, "Core i5 (Lynnfield)", "45 nm" }, + { 6, 14, -1, -1, 30, -1, -1, -1, { "Core(TM) i7 [QX] [789]##", 10 }, "Core i7 (Clarksfield)", "45 nm" }, + { 6, 14, -1, -1, 30, -1, -1, -1, { "Core(TM) [QX] [789]##", 8 }, "Core i7 (Clarksfield)", "45 nm" }, + + /* Bonnell CPUs (2008, Atom, 45 nm): https://en.wikipedia.org/wiki/Bonnell_(microarchitecture) */ + { 6, 6, -1, -1, 38, -1, -1, -1, { "Atom(TM) E6##T", 8 }, "Atom (Tunnel Creek)", "45 nm" }, + { 6, 6, -1, -1, 38, -1, -1, -1, { "Atom(TM) E6##", 6 }, "Atom (Tunnel Creek)", "45 nm" }, + { 6, 6, -1, -1, 38, -1, -1, -1, { "Atom(TM) E6##C", 8 }, "Atom (Stellarton)", "45 nm" }, + { 6, 12, -1, -1, 28, -1, -1, -1, { "Atom(TM) Z5##", 6 }, "Atom (Silverthorne)", "45 nm" }, + { 6, 12, -1, -1, 28, -1, -1, -1, { "Atom(TM) N2##", 6 }, "Atom (Diamondville)", "45 nm" }, + { 6, 12, -1, -1, 28, -1, -1, -1, { "Atom(TM) [23]##", 6 }, "Atom (Diamondville)", "45 nm" }, + { 6, 6, -1, -1, 38, -1, -1, -1, { "Atom(TM) Z6##", 6 }, "Atom (Lincroft)", "45 nm" }, + { 6, 12, -1, -1, 28, -1, -1, -1, { "Atom(TM) Z6##", 6 }, "Atom (Lincroft)", "45 nm" }, + { 6, 12, -1, -1, 28, -1, -1, -1, { "Atom(TM) [ND][45]##", 6 }, "Atom (Pineview)", "45 nm" }, + + /* Westmere CPUs (2010, 1st Core i gen, 32 nm): https://en.wikipedia.org/wiki/Westmere_(microarchitecture) */ + { 6, 14, -1, -1, 46, -1, -1, -1, { "Xeon(R) [EXL]75##", 6 }, "Xeon 7000 (Beckton)", "32 nm" }, + { 6, 14, -1, -1, 46, -1, -1, -1, { "Xeon(R) E65##", 6 }, "Xeon 6000 (Beckton)", "32 nm" }, + { 6, 14, -1, -1, 46, -1, -1, -1, { "Xeon(R) [XELW]5[56]##", 6 }, "Xeon 5000 (Beckton)", "32 nm" }, + { 6, 14, -1, -1, 46, -1, -1, -1, { "Xeon(R) [XLW]3[456]###", 6 }, "Xeon 3000 (Beckton)", "32 nm" }, + { 6, 15, -1, -1, 47, -1, -1, -1, { "Xeon(R) E7-#8##", 6 }, "Xeon E7 (Westmere-EX)", "32 nm" }, + { 6, 12, -1, -1, 44, -1, -1, -1, { "Xeon(R) [XEL]5###", 6 }, "Xeon (Westmere-EP)", "32 nm" }, + { 6, 12, -1, -1, 44, -1, -1, -1, { "Xeon(R) W3###", 6 }, "Xeon (Gulftown)", "32 nm" }, + { 6, 12, -1, -1, 44, -1, -1, -1, { "Core(TM) i7 X 9##", 10 }, "Core i7 Extreme (Gulftown)", "32 nm" }, + { 6, 12, -1, -1, 44, -1, -1, -1, { "Core(TM) i7 9##", 8 }, "Core i7 (Gulftown)", "32 nm" }, + { 6, 5, -1, -1, 37, -1, -1, -1, { "Xeon(R) L3###", 6 }, "Xeon (Clarkdale)", "32 nm" }, + { 6, 5, -1, -1, 37, -1, -1, -1, { "Core(TM) i5 6##", 8 }, "Core i5 (Clarkdale)", "32 nm" }, + { 6, 5, -1, -1, 37, -1, -1, -1, { "Core(TM) i3 5##", 8 }, "Core i3 (Clarkdale)", "32 nm" }, + { 6, 5, -1, -1, 37, -1, -1, -1, { "Pentium(R) G6###", 6 }, "Pentium (Clarkdale)", "32 nm" }, + { 6, 5, -1, -1, 37, -1, -1, -1, { "Celeron(R) G1###", 6 }, "Celeron (Clarkdale)", "32 nm" }, + { 6, 5, -1, -1, 37, -1, -1, -1, { "Core(TM) i7 M 6##", 8 }, "Core i7 (Arrandale)", "32 nm" }, + { 6, 5, -1, -1, 37, -1, -1, -1, { "Core(TM) i5 M [45]##", 8 }, "Core i5 (Arrandale)", "32 nm" }, + { 6, 5, -1, -1, 37, -1, -1, -1, { "Core(TM) i3 M 3##", 8 }, "Core i3 (Arrandale)", "32 nm" }, + { 6, 5, -1, -1, 37, -1, -1, -1, { "Pentium(R) P6###", 6 }, "Pentium (Arrandale)", "32 nm" }, + { 6, 5, -1, -1, 37, -1, -1, -1, { "Pentium(R) 5U###", 6 }, "Pentium (Arrandale)", "32 nm" }, + { 6, 5, -1, -1, 37, -1, -1, -1, { "Celeron(R) P4###", 6 }, "Celeron (Arrandale)", "32 nm" }, + { 6, 5, -1, -1, 37, -1, -1, -1, { "Celeron(R) U3###", 6 }, "Celeron (Arrandale)", "32 nm" }, + + /* Saltwell CPUs (2011, Atom, 32 nm): https://en.wikipedia.org/wiki/Bonnell_(microarchitecture)#Third_generation_cores */ + { 6, 12, -1, -1, -1, -1, -1, -1, { "Atom(TM) [ND]2###", 6 }, "Atom (Cedarview)", "32 nm" }, + { 6, 6, -1, -1, 54, -1, -1, -1, { "Atom(TM) [ND]2###", 6 }, "Atom (Cedarview)", "32 nm" }, + { 6, 7, -1, -1, 39, -1, -1, -1, { "Atom(TM) Z2###", 6 }, "Atom (Penwell)", "32 nm" }, + + /* Sandy Bridge CPUs (2011, 2nd Core i gen, 32 nm): https://en.wikipedia.org/wiki/Sandy_Bridge */ + { 6, 10, -1, -1, 42, -1, -1, -1, { "Xeon(R) E5####[LW]", 8 }, "Xeon E5 (Sandy Bridge)", "32 nm" }, + { 6, 10, -1, -1, 42, -1, -1, -1, { "Xeon(R) E5####", 6 }, "Xeon E5 (Sandy Bridge)", "32 nm" }, + { 6, 10, -1, -1, 42, -1, -1, -1, { "Xeon(R) E3####[CL]", 8 }, "Xeon E3 (Sandy Bridge)", "32 nm" }, + { 6, 10, -1, -1, 42, -1, -1, -1, { "Xeon(R) E3####", 6 }, "Xeon E3 (Sandy Bridge)", "32 nm" }, + { 6, 10, -1, -1, 42, -1, -1, -1, { "Core(TM) i7-2###", 8 }, "Core i7 (Sandy Bridge)", "32 nm" }, + { 6, 10, -1, -1, 42, -1, -1, -1, { "Core(TM) i5-2###", 8 }, "Core i5 (Sandy Bridge)", "32 nm" }, + { 6, 10, -1, -1, 42, -1, -1, -1, { "Core(TM) i3-2###", 8 }, "Core i3 (Sandy Bridge)", "32 nm" }, + { 6, 10, -1, -1, 42, -1, -1, -1, { "Pentium(R) G[68]##", 6 }, "Pentium (Sandy Bridge)", "32 nm" }, + { 6, 10, -1, -1, 42, -1, -1, -1, { "Celeron(R) G[45]##", 6 }, "Celeron (Sandy Bridge)", "32 nm" }, + { 6, 13, -1, -1, 45, -1, -1, -1, { "Core(TM) i7-3###[KX]", 10 }, "Core i7 Extreme (Sandy Bridge-E)", "32 nm" }, + { 6, 13, -1, -1, 45, -1, -1, -1, { "Xeon(R) E5-####", 4 }, "Xeon E5 (Sandy Bridge-E)", "32 nm" }, + { 6, 13, -1, -1, 45, -1, -1, -1, { "Xeon(R) E3-####", 4 }, "Xeon E3 (Sandy Bridge-E)", "32 nm" }, + + /* Ivy Bridge CPUs (2012, 3rd Core i gen, 22 nm): https://en.wikipedia.org/wiki/Ivy_Bridge_(microarchitecture) */ + { 6, 10, -1, -1, 58, -1, -1, -1, { "Xeon(R) E7-####L v2", 8 }, "Xeon E7 (Ivy Bridge)", "22 nm" }, + { 6, 10, -1, -1, 58, -1, -1, -1, { "Xeon(R) E7-#### v2", 6 }, "Xeon E7 (Ivy Bridge)", "22 nm" }, + { 6, 10, -1, -1, 58, -1, -1, -1, { "Xeon(R) E5-####[LW] v2", 8 }, "Xeon E5 (Ivy Bridge)", "22 nm" }, + { 6, 10, -1, -1, 58, -1, -1, -1, { "Xeon(R) E5-#### v2", 6 }, "Xeon E5 (Ivy Bridge)", "22 nm" }, + { 6, 10, -1, -1, 58, -1, -1, -1, { "Xeon(R) E3-####[CL] v2", 8 }, "Xeon E3 (Ivy Bridge)", "22 nm" }, + { 6, 10, -1, -1, 58, -1, -1, -1, { "Xeon(R) E3-#### v2", 6 }, "Xeon E3 (Ivy Bridge)", "22 nm" }, + { 6, 10, -1, -1, 58, -1, -1, -1, { "Core(TM) i7-3###", 8 }, "Core i7 (Ivy Bridge)", "22 nm" }, + { 6, 10, -1, -1, 58, -1, -1, -1, { "Core(TM) i5-3###", 8 }, "Core i5 (Ivy Bridge)", "22 nm" }, + { 6, 10, -1, -1, 58, -1, -1, -1, { "Core(TM) i3-3###", 8 }, "Core i3 (Ivy Bridge)", "22 nm" }, + { 6, 10, -1, -1, 58, -1, -1, -1, { "Pentium(R) G2###", 6 }, "Pentium (Ivy Bridge)", "22 nm" }, + { 6, 10, -1, -1, 58, -1, -1, -1, { "Celeron(R) G1###", 6 }, "Celeron (Ivy Bridge)", "22 nm" }, + { 6, 14, -1, -1, 62, -1, -1, -1, { "Xeon(R) E7-#### v2", 6 }, "Xeon E7 (Ivy Bridge-E)", "22 nm" }, + { 6, 14, -1, -1, 62, -1, -1, -1, { "Xeon(R) E5-#### v2", 6 }, "Xeon E5 (Ivy Bridge-E)", "22 nm" }, + { 6, 14, -1, -1, 62, -1, -1, -1, { "Xeon(R) E3-#### v2", 6 }, "Xeon E3 (Ivy Bridge-E)", "22 nm" }, + { 6, 14, -1, -1, 62, -1, -1, -1, { "Core(TM) i7-4###X", 10 }, "Core i7 Extreme (Ivy Bridge-E)", "22 nm" }, + { 6, 14, -1, -1, 62, -1, -1, -1, { "Core(TM) i7-4###K", 8 }, "Core i7 (Ivy Bridge-E)", "22 nm" }, + + /* Silvermont CPUs (2013, Atom, 22 nm): https://en.wikipedia.org/wiki/Silvermont */ + { 6, 7, -1, -1, 55, -1, -1, -1, { "Pentium(R) J2###", 6 }, "Pentium (Bay Trail-D)", "22 nm" }, + { 6, 7, -1, -1, 55, -1, -1, -1, { "Celeron(R) J1###", 6 }, "Celeron (Bay Trail-D)", "22 nm" }, + { 6, 7, -1, -1, 55, -1, -1, -1, { "Pentium(R) N3###", 6 }, "Pentium (Bay Trail-M)", "22 nm" }, + { 6, 7, -1, -1, 55, -1, -1, -1, { "Celeron(R) N2###", 6 }, "Celeron (Bay Trail-M)", "22 nm" }, + { 6, 7, -1, -1, 55, -1, -1, -1, { "Atom(TM) Z3###", 6 }, "Atom (Bay Trail-T)", "22 nm" }, + { 6, 7, -1, -1, 55, -1, -1, -1, { "Atom(TM) E3###", 6 }, "Atom (Bay Trail-I)", "22 nm" }, + { 6, 13, -1, -1, 77, -1, -1, -1, { "Atom(TM) C2##0", 8 }, "Atom (Avoton)", "22 nm" }, + { 6, 13, -1, -1, 77, -1, -1, -1, { "Atom(TM) C2##[68]", 8 }, "Atom (Rangeley)", "22 nm" }, + + /* Haswell CPUs (2013, 4th Core i gen, 22 nm): https://en.wikipedia.org/wiki/Haswell_(microarchitecture) */ + { 6, 12, -1, -1, 60, -1, -1, -1, { "Xeon(R) E7-####L v3", 8 }, "Xeon E7 (Haswell)", "22 nm" }, + { 6, 12, -1, -1, 60, -1, -1, -1, { "Xeon(R) E7-#### v3", 6 }, "Xeon E7 (Haswell)", "22 nm" }, + { 6, 12, -1, -1, 60, -1, -1, -1, { "Xeon(R) E5-####[ABLW] v3", 8 }, "Xeon E5 (Haswell)", "22 nm" }, + { 6, 12, -1, -1, 60, -1, -1, -1, { "Xeon(R) E5-#### v3", 6 }, "Xeon E5 (Haswell)", "22 nm" }, + { 6, 12, -1, -1, 60, -1, -1, -1, { "Xeon(R) E3-####L v3", 8 }, "Xeon E3 (Haswell)", "22 nm" }, + { 6, 12, -1, -1, 60, -1, -1, -1, { "Xeon(R) E3-#### v3", 6 }, "Xeon E3 (Haswell)", "22 nm" }, + { 6, 12, -1, -1, 60, -1, -1, -1, { "Core(TM) i7-4###", 8 }, "Core i7 (Haswell)", "22 nm" }, + { 6, 12, -1, -1, 60, -1, -1, -1, { "Core(TM) i5-4###", 8 }, "Core i5 (Haswell)", "22 nm" }, + { 6, 12, -1, -1, 60, -1, -1, -1, { "Core(TM) i3-4###", 8 }, "Core i3 (Haswell)", "22 nm" }, + { 6, 12, -1, -1, 60, -1, -1, -1, { "Pentium(R) G3###", 6 }, "Pentium (Haswell)", "22 nm" }, + { 6, 12, -1, -1, 60, -1, -1, -1, { "Celeron(R) G1###", 6 }, "Celeron (Haswell)", "22 nm" }, + { 6, 15, -1, -1, 63, -1, -1, -1, { "Core(TM) i7-5###[KX]", 8 }, "Core i7 Extreme (Haswell)", "22 nm" }, + { 6, 5, -1, -1, 69, -1, -1, -1, { "Core(TM) i7-4###", 8 }, "Core i7 (Haswell)", "22 nm" }, + { 6, 5, -1, -1, 69, -1, -1, -1, { "Core(TM) i5-4###", 8 }, "Core i5 (Haswell)", "22 nm" }, + { 6, 5, -1, -1, 69, -1, -1, -1, { "Core(TM) i3-4###", 8 }, "Core i3 (Haswell)", "22 nm" }, + { 6, 6, -1, -1, 70, -1, -1, -1, { "Core(TM) i7-4###R", 10 }, "Core i7 (Haswell-H)", "22 nm" }, /* GT3e */ + { 6, 6, -1, -1, 70, -1, -1, -1, { "Core(TM) i5-4###R", 10 }, "Core i5 (Haswell-H)", "22 nm" }, /* GT3e */ + { 6, 5, -1, -1, 69, -1, -1, -1, { "Core(TM) i7-4###U", 10 }, "Core i7 (Haswell-ULT)", "22 nm" }, + { 6, 5, -1, -1, 69, -1, -1, -1, { "Core(TM) i5-4###U", 10 }, "Core i5 (Haswell-ULT)", "22 nm" }, + { 6, 5, -1, -1, 69, -1, -1, -1, { "Core(TM) i3-4###U", 10 }, "Core i3 (Haswell-ULT)", "22 nm" }, + { 6, 5, -1, -1, 69, -1, -1, -1, { "Core(TM) i7-4###Y", 10 }, "Core i7 (Haswell-ULX)", "22 nm" }, + { 6, 5, -1, -1, 69, -1, -1, -1, { "Core(TM) i5-4###Y", 10 }, "Core i5 (Haswell-ULX)", "22 nm" }, + { 6, 5, -1, -1, 69, -1, -1, -1, { "Core(TM) i3-4###Y", 10 }, "Core i3 (Haswell-ULX)", "22 nm" }, + + /* Broadwell CPUs (2014, 5th Core i gen, 14 nm): https://en.wikipedia.org/wiki/Broadwell_(microarchitecture) */ + { 6, 6, -1, -1, 86, -1, -1, -1, { "Xeon(R) D-15##", 6 }, "Xeon D (Broadwell)", "14 nm" }, + { 6, 6, -1, -1, 86, -1, -1, -1, { "Pentium(R) D15##", 6 }, "Pentium D (Broadwell)", "14 nm" }, + { 6, 7, -1, -1, 71, 4, -1, -1, { "Core(TM) i7-5###[CR]", 10 }, "Core i7 (Broadwell-H)", "14 nm" }, + { 6, 7, -1, -1, 71, 4, -1, -1, { "Core(TM) i5-5###[CR]", 10 }, "Core i5 (Broadwell-H)", "14 nm" }, + { 6, 13, -1, -1, 61, 4, -1, -1, { "Core(TM) i7-5###HQ", 12 }, "Core i7 (Broadwell-U)", "14 nm" }, + { 6, 13, -1, -1, 61, 2, -1, -1, { "Core(TM) i7-5###U", 10 }, "Core i7 (Broadwell-U)", "14 nm" }, + { 6, 13, -1, -1, 61, 2, -1, -1, { "Core(TM) i5-5###[HU]", 10 }, "Core i5 (Broadwell-U)", "14 nm" }, + { 6, 13, -1, -1, 61, 2, -1, -1, { "Core(TM) i3-5###U", 10 }, "Core i3 (Broadwell-U)", "14 nm" }, + { 6, 13, -1, -1, 61, 2, -1, -1, { "Pentium(R) 3###U", 6 }, "Pentium (Broadwell-U)", "14 nm" }, + { 6, 13, -1, -1, 61, 2, -1, -1, { "Celeron(R) 3###U", 6 }, "Celeron (Broadwell-U)", "14 nm" }, + { 6, 13, -1, -1, 61, 2, -1, -1, { "5Y##", 4 }, "Core M (Broadwell-Y)", "14 nm" }, + { 6, 15, -1, -1, 79, -1, -1, -1, { "Xeon(R) E7-#### v4", 6 }, "Xeon E7 (Broadwell)", "14 nm" }, + { 6, 15, -1, -1, 79, -1, -1, -1, { "Xeon(R) E5-####[ACLPRW] v4", 8 }, "Xeon E5 (Broadwell)", "14 nm" }, + { 6, 15, -1, -1, 79, -1, -1, -1, { "Xeon(R) E5-#### v4", 6 }, "Xeon E5 (Broadwell)", "14 nm" }, + { 6, 15, -1, -1, 79, -1, -1, -1, { "Xeon(R) E3-####L v4", 8 }, "Xeon E3 (Broadwell)", "14 nm" }, + { 6, 15, -1, -1, 79, -1, -1, -1, { "Xeon(R) E3-#### v4", 6 }, "Xeon E3 (Broadwell)", "14 nm" }, + { 6, 15, -1, -1, 79, 4, -1, -1, { "Core(TM) i7-6###[KX]", 10 }, "Core i7 (Broadwell-E)", "14 nm" }, + + /* Airmont CPUs (2014, Atom, 14 nm): https://en.wikipedia.org/wiki/Silvermont#List_of_Airmont_processors */ + { 6, 12, -1, -1, 76, -1, -1, -1, { "Pentium(R) [JN]3###", 6 }, "Pentium (Braswell)", "14 nm" }, + { 6, 12, -1, -1, 76, -1, -1, -1, { "Celeron(R) [JN]3###", 6 }, "Celeron (Braswell)", "14 nm" }, + { 6, 12, -1, -1, 76, 4, -1, -1, { "Atom(TM) x7-Z8###", 8 }, "Atom x7 (Cherry Trail)", "14 nm" }, + { 6, 12, -1, -1, 76, 4, -1, -1, { "Atom(TM) x5-Z8###", 8 }, "Atom x5 (Cherry Trail)", "14 nm" }, + { 6, 5, -1, -1, 117, -1, -1, -1, { "Spreadtrum", 2 }, "Spreadtrum (Airmont)", "14 nm" }, /* Spreadtrum SC9853I-IA */ + + /* Skylake (client) CPUs (2015, 6th Core i gen, 14 nm): https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(client) */ + { 6, 14, -1, -1, 94, 4, -1, -1, { "Core(TM) i7-6###", 8 }, "Core i7 (Skylake)", "14 nm" }, + { 6, 14, -1, -1, 94, 4, -1, -1, { "Core(TM) i5-6###", 8 }, "Core i5 (Skylake)", "14 nm" }, + { 6, 14, -1, -1, 94, 2, -1, -1, { "Core(TM) i3-6###", 8 }, "Core i3 (Skylake)", "14 nm" }, + { 6, 14, -1, -1, 94, 2, -1, -1, { "Pentium(R) G4###", 6 }, "Pentium (Skylake)", "14 nm" }, + { 6, 14, -1, -1, 94, 2, -1, -1, { "Celeron(R) G3###", 6 }, "Celeron (Skylake)", "14 nm" }, + { 6, 14, -1, -1, 78, 2, -1, -1, { "Core(TM) m7-6Y##", 8 }, "Core m7 (Skylake)", "14 nm" }, + { 6, 14, -1, -1, 78, 2, -1, -1, { "Core(TM) m5-6Y##", 8 }, "Core m5 (Skylake)", "14 nm" }, + { 6, 14, -1, -1, 78, 2, -1, -1, { "Core(TM) m3-6Y##", 8 }, "Core m3 (Skylake)", "14 nm" }, + { 6, 14, -1, -1, 78, 2, -1, -1, { "Pentium(R) 4###[UY]", 6 }, "Pentium (Skylake)", "14 nm" }, + { 6, 14, -1, -1, 78, 2, -1, -1, { "Celeron(R) 3###U", 6 }, "Celeron (Skylake)", "14 nm" }, + { 6, 14, -1, -1, 78, 2, -1, -1, { "Celeron(R) G3###E", 8 }, "Celeron (Skylake)", "14 nm" }, + { 6, 5, -1, -1, 85, -1, -1, -1, { "Core(TM) i9-7###X", 10 }, "Core i9 (Skylake-X)", "14 nm" }, + { 6, 5, -1, -1, 85, -1, -1, -1, { "Core(TM) i7-7###X", 10 }, "Core i7 (Skylake-X)", "14 nm" }, /* Core i7 7800X + 7820X */ + { 6, 5, -1, -1, 85, -1, -1, -1, { "Core(TM) i9-9###X", 10 }, "Core i9 (Skylake-X)", "14 nm" }, + { 6, 5, -1, -1, 85, -1, -1, -1, { "Core(TM) i7-9###X", 10 }, "Core i7 (Skylake-X)", "14 nm" }, /* Core i7 9800X */ + { 6, 14, -1, -1, 94, -1, -1, -1, { "Xeon(R) W-#1##X", 8 }, "Xeon (Skylake-X)", "14 nm" }, + /* Skylake (server) CPUs (2017, 1st Xeon Scalable gen, 14 nm): https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(server) */ + { 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) D-#1##", 6 }, "Xeon D (Skylake-D)", "14 nm" }, + { 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) E3-####[ML] v5", 8 }, "Xeon E3 (Skylake-S)", "14 nm" }, + { 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) E3-#### v5", 6 }, "Xeon E3 (Skylake-S)", "14 nm" }, + { 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) W-#1##", 6 }, "Xeon W (Skylake-W)", "14 nm" }, + { 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) Platinum #1##", 6 }, "Xeon Platinum (Skylake-SP)", "14 nm" }, + { 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) Gold #1##", 6 }, "Xeon Gold (Skylake-SP)", "14 nm" }, + { 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) Silver #1##", 6 }, "Xeon Silver (Skylake-SP)", "14 nm" }, + { 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) Bronze #1##", 6 }, "Xeon Bronze (Skylake-SP)", "14 nm" }, + { 6, 5, -1, -1, 85, -1, -1, -1, { "Montage(R) Jintide(R)", 4 }, "Jintide (Skylake-SP)", "14 nm" }, /* Montage(R) Jintide(R) C2460 */ + /* Kaby Lake CPUs (2016, 7th Core i gen, 14+ nm): https://en.wikipedia.org/wiki/Kaby_Lake */ + { 6, 14, -1, -1, 158, 4, -1, -1, { "Core(TM) i7-7###", 8 }, "Core i7 (Kaby Lake)", "14+ nm" }, + { 6, 14, -1, -1, 158, 4, -1, -1, { "Core(TM) i5-7###", 8 }, "Core i5 (Kaby Lake)", "14+ nm" }, + { 6, 14, -1, -1, 158, 2, -1, -1, { "Core(TM) i3-7###", 8 }, "Core i3 (Kaby Lake)", "14+ nm" }, + { 6, 14, -1, -1, 158, 2, -1, -1, { "Pentium(R) G4###", 6 }, "Pentium (Kaby Lake)", "14+ nm" }, + { 6, 14, -1, -1, 158, 2, -1, -1, { "Celeron(R) G3###", 6 }, "Celeron (Kaby Lake)", "14+ nm" }, + { 6, 14, -1, -1, 158, 4, -1, -1, { "Core(TM) i7-7###X", 10 }, "Core i7 (Kaby Lake-X)", "14+ nm" }, + { 6, 14, -1, -1, 158, 4, -1, -1, { "Core(TM) i5-7###X", 10 }, "Core i5 (Kaby Lake-X)", "14+ nm" }, + { 6, 14, -1, -1, 142, 2, -1, -1, { "Core(TM) i7-7.##", 8 }, "Core i7 (Kaby Lake-U)", "14+ nm" }, + { 6, 14, -1, -1, 142, 2, -1, -1, { "Core(TM) i5-7.##", 8 }, "Core i5 (Kaby Lake-U)", "14+ nm" }, + { 6, 14, -1, -1, 142, 2, -1, -1, { "Core(TM) i3-7.##", 8 }, "Core i3 (Kaby Lake-U)", "14+ nm" }, + { 6, 14, -1, -1, 142, 2, -1, -1, { "Core(TM) m3-7.##", 8 }, "Core m3 (Kaby Lake-U)", "14+ nm" }, + { 6, 14, -1, -1, 142, 2, -1, -1, { "Pentium(R) 441#[UY]", 8 }, "Pentium Gold (Kaby Lake-U)", "14+ nm" }, + { 6, 14, -1, -1, 142, 2, -1, -1, { "Celeron(R) 3###[UY]", 6 }, "Celeron (Kaby Lake-U)", "14+ nm" }, + { 6, 14, -1, -1, 158, 4, -1, -1, { "Core(TM) i7-8###G", 10 }, "Core i7 (Kaby Lake-G)", "14+ nm" }, + { 6, 14, -1, -1, 158, 4, -1, -1, { "Core(TM) i5-8###G", 10 }, "Core i5 (Kaby Lake-G)", "14+ nm" }, + { 6, 14, -1, -1, 142, 4, -1, -1, { "Core(TM) i7-8##0U", 10 }, "Core i7 (Kaby Lake-R)", "14+ nm" }, /* i7-8550U + i7-8650U */ + { 6, 14, -1, -1, 142, 4, -1, -1, { "Core(TM) i5-8##0U", 10 }, "Core i5 (Kaby Lake-R)", "14+ nm" }, /* i5-8250U + i5-8350U */ + { 6, 14, -1, -1, 142, 2, -1, -1, { "Core(TM) i3-8##0U", 10 }, "Core i3 (Kaby Lake-R)", "14+ nm" }, /* i3-8130U */ + { 6, 14, -1, -1, 142, 2, -1, -1, { "Pentium(R) 4###U", 6 }, "Pentium Gold (Kaby Lake-R)", "14+ nm" }, /* Pentium 4417U */ + { 6, 14, -1, -1, 142, 2, -1, -1, { "Celeron(R) 3###U", 6 }, "Celeron (Kaby Lake-R)", "14+ nm" }, /* Celeron 3867U */ + /* Coffee Lake CPUs (2017, 8th Core i gen, 14++ nm): https://en.wikipedia.org/wiki/Coffee_Lake */ + { 6, 14, -1, -1, 158, 6, -1, -1, { "Core(TM) i7-8###", 8 }, "Core i7 (Coffee Lake-S)", "14++ nm" }, + { 6, 14, -1, -1, 158, 6, -1, -1, { "Core(TM) i5-8###", 8 }, "Core i5 (Coffee Lake-S)", "14++ nm" }, + { 6, 14, -1, -1, 158, 4, -1, -1, { "Core(TM) i3-8###", 8 }, "Core i3 (Coffee Lake-S)", "14++ nm" }, + { 6, 14, -1, -1, 158, 2, -1, -1, { "Pentium(R) G5###", 6 }, "Pentium Gold (Coffee Lake-S)", "14++ nm" }, + { 6, 14, -1, -1, 158, 2, -1, -1, { "Celeron(R) G4###", 6 }, "Celeron (Coffee Lake-S)", "14++ nm" }, + { 6, 14, -1, -1, 158, 6, -1, -1, { "Xeon(R) E-21##M", 8 }, "Xeon E (Coffee Lake-H)", "14++ nm" }, + { 6, 14, -1, -1, 158, 6, -1, -1, { "Core(TM) i9-8###[HB]", 10 }, "Core i9 (Coffee Lake-H)", "14++ nm" }, + { 6, 14, -1, -1, 158, 6, -1, -1, { "Core(TM) i7-8###[HB]", 10 }, "Core i7 (Coffee Lake-H)", "14++ nm" }, + { 6, 14, -1, -1, 158, 4, -1, -1, { "Core(TM) i5-8###[HB]", 10 }, "Core i5 (Coffee Lake-H)", "14++ nm" }, + { 6, 14, -1, -1, 158, 4, -1, -1, { "Core(TM) i5-8###[HB]", 10 }, "Core i5 (Coffee Lake-H)", "14++ nm" }, + { 6, 14, -1, -1, 158, 4, -1, -1, { "Core(TM) i3-8###[HB]", 10 }, "Core i3 (Coffee Lake-H)", "14++ nm" }, + { 6, 14, -1, -1, 158, 4, -1, -1, { "Core(TM) i7-8###U", 10 }, "Core i7 (Coffee Lake-U)", "14++ nm" }, + { 6, 14, -1, -1, 158, 4, -1, -1, { "Core(TM) i5-8###U", 10 }, "Core i5 (Coffee Lake-U)", "14++ nm" }, + { 6, 14, -1, -1, 158, 2, -1, -1, { "Core(TM) i3-8###U", 10 }, "Core i3 (Coffee Lake-U)", "14++ nm" }, + /* Coffee Lake Refresh CPUs (2018, 9th Core i gen, 14++ nm): https://en.wikipedia.org/wiki/Coffee_Lake#List_of_9th_generation_Coffee_Lake_processors_(Coffee_Lake_Refresh) */ + { 6, 14, -1, -1, 158, 8, -1, -1, { "Xeon(R) E-2###", 6 }, "Xeon E (Coffee Lake-S WS)", "14++ nm" }, + { 6, 14, -1, -1, 158, 8, -1, -1, { "CC###", 4 }, "CC (Coffee Lake)", "14++ nm" }, /* CC150 */ + { 6, 14, -1, -1, 158, 8, -1, -1, { "Core(TM) i9-9###", 8 }, "Core i9 (Coffee Lake-S)", "14++ nm" }, + { 6, 14, -1, -1, 158, 8, -1, -1, { "Core(TM) i7-9###", 8 }, "Core i7 (Coffee Lake-S)", "14++ nm" }, + { 6, 14, -1, -1, 158, 6, -1, -1, { "Core(TM) i5-9###", 8 }, "Core i5 (Coffee Lake-S)", "14++ nm" }, + { 6, 14, -1, -1, 158, 4, -1, -1, { "Core(TM) i3-9###", 8 }, "Core i3 (Coffee Lake-S)", "14++ nm" }, + { 6, 14, -1, -1, 158, 2, -1, -1, { "Pentium(R) Gold G5###", 8 }, "Pentium Gold (Coffee Lake-S)", "14++ nm" }, + { 6, 14, -1, -1, 158, 2, -1, -1, { "Celeron(R) G4###", 6 }, "Celeron (Coffee Lake-S)", "14++ nm" }, + { 6, 14, -1, -1, 158, -1, -1, -1, { "Xeon(R) E-22##M", 8 }, "Xeon E (Coffee Lake-H Refresh)", "14++ nm" }, + { 6, 14, -1, -1, 158, 8, -1, -1, { "Core(TM) i9-9###H", 10 }, "Core i9 (Coffee Lake-H Refresh)", "14++ nm" }, + { 6, 14, -1, -1, 158, 6, -1, -1, { "Core(TM) i7-9###H", 10 }, "Core i7 (Coffee Lake-H Refresh)", "14++ nm" }, + { 6, 14, -1, -1, 158, 4, -1, -1, { "Core(TM) i5-9###H", 10 }, "Core i5 (Coffee Lake-H Refresh)", "14++ nm" }, + /* Whiskey Lake CPUs (2018, 8th Core i gen, 14++ nm): https://en.wikipedia.org/wiki/Whiskey_Lake */ + { 6, 14, -1, -1, 142, 4, -1, -1, { "Core(TM) i7-8##5U", 10 }, "Core i7 (Whiskey Lake-U)", "14++ nm" }, + { 6, 14, -1, -1, 142, 4, -1, -1, { "Core(TM) i5-8##5U", 10 }, "Core i5 (Whiskey Lake-U)", "14++ nm" }, + { 6, 14, -1, -1, 142, 2, -1, -1, { "Core(TM) i3-8##5U", 10 }, "Core i3 (Whiskey Lake-U)", "14++ nm" }, + { 6, 14, -1, -1, 142, 2, -1, -1, { "Pentium(R) 5###U", 6 }, "Pentium Gold (Whiskey Lake-U)", "14++ nm" }, + { 6, 14, -1, -1, 142, 2, -1, -1, { "Celeron(R) 4###U", 6 }, "Celeron (Whiskey Lake-U)", "14++ nm" }, + /* Amber Lake CPUs (2018, 8th Core i gen, 14++ nm): https://en.wikipedia.org/wiki/Kaby_Lake#Amber_Lake */ + { 6, 14, -1, -1, 142, 4, -1, -1, { "Core(TM) i7-8###Y", 10 }, "Core i7 (Amber Lake-Y)", "14+ nm" }, /* i7-8500Y */ + { 6, 14, -1, -1, 142, 4, -1, -1, { "Core(TM) i5-8###Y", 10 }, "Core i5 (Amber Lake-Y)", "14+ nm" }, /* i5-8200Y + i5-82010Y + i5-8310Y */ + { 6, 14, -1, -1, 142, 2, -1, -1, { "Core(TM) m3-8###Y", 10 }, "Core m3 (Amber Lake-Y)", "14+ nm" }, /* m3-8100Y */ + { 6, 14, -1, -1, 142, 2, -1, -1, { "Pentium(R) 442#Y", 8 }, "Pentium Gold (Amber Lake-Y)", "14+ nm" }, /* Pentium 4425Y */ + { 6, 14, -1, -1, 142, 4, -1, -1, { "Core(TM) i7-10###Y", 10 }, "Core i7 (Amber Lake-Y)", "14+ nm" }, /* i7-10510Y */ + { 6, 14, -1, -1, 142, 4, -1, -1, { "Core(TM) i5-10###Y", 10 }, "Core i5 (Amber Lake-Y)", "14+ nm" }, /* i5-10210Y + i5-10310Y + i5-8310Y */ + { 6, 14, -1, -1, 142, 2, -1, -1, { "Core(TM) i3-10###Y", 10 }, "Core i3 (Amber Lake-Y)", "14+ nm" }, /* i3-10100Y + i3-10110Y */ + { 6, 14, -1, -1, 142, 2, -1, -1, { "Pentium(R) 65##Y", 6 }, "Pentium Gold (Amber Lake-Y)", "14+ nm" }, /* Pentium 6500Y */ + /* Cascade Lake CPUs (2019, 2nd Xeon Scalable gen, 14++ nm): https://en.wikichip.org/wiki/intel/microarchitectures/cascade_lake */ + { 6, 5, 7, -1, 85, -1, -1, -1, { "Core(TM) i9-10###X", 10 }, "Core i9 (Cascade Lake-X)", "14++ nm" }, + { 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) W-#[23]##", 6 }, "Xeon W (Cascade Lake-W)", "14++ nm" }, + { 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) Platinum #2##", 6 }, "Xeon Platinum (Cascade Lake-SP)", "14++ nm" }, + { 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) Gold #2##", 6 }, "Xeon Gold (Cascade Lake-SP)", "14++ nm" }, + { 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) Silver #2##", 6 }, "Xeon Silver (Cascade Lake-SP)", "14++ nm" }, + { 6, 5, -1, -1, 85, -1, -1, -1, { "Xeon(R) Bronze #2##", 6 }, "Xeon Bronze (Cascade Lake-SP)", "14++ nm" }, + /* Comet Lake CPUs (2019, 10th Core i gen, 14++ nm): https://en.wikipedia.org/wiki/Comet_Lake */ + { 6, 5, -1, -1, 165, -1, -1, -1, { "Xeon(R) W-12##", 6 }, "Xeon W (Comet Lake-S)", "14++ nm" }, + { 6, 5, -1, -1, 165, 10, -1, -1, { "Core(TM) i9-10###", 8 }, "Core i9 (Comet Lake-S)", "14++ nm" }, + { 6, 5, -1, -1, 165, 8, -1, -1, { "Core(TM) i7-10###", 8 }, "Core i7 (Comet Lake-S)", "14++ nm" }, + { 6, 5, -1, -1, 165, 6, -1, -1, { "Core(TM) i5-10###", 8 }, "Core i5 (Comet Lake-S)", "14++ nm" }, + { 6, 5, -1, -1, 165, 4, -1, -1, { "Core(TM) i3-10###", 8 }, "Core i3 (Comet Lake-S)", "14++ nm" }, + { 6, 5, -1, -1, 165, 2, -1, -1, { "Pentium(R) Gold G6###", 8 }, "Pentium Gold (Comet Lake-S)", "14++ nm" }, + { 6, 5, -1, -1, 165, 2, -1, -1, { "Celeron(R) G5###", 6 }, "Celeron (Comet Lake-S)", "14++ nm" }, + { 6, 6, -1, -1, 166, 6, -1, -1, { "Core(TM) i7-10###U", 10 }, "Core i7 (Comet Lake-U)", "14++ nm" }, + { 6, 14, 12, -1, 142, 6, -1, -1, { "Core(TM) i7-10###U", 10 }, "Core i7 (Comet Lake-U)", "14++ nm" }, + { 6, 14, 12, -1, 142, 4, -1, -1, { "Core(TM) i7-10###U", 10 }, "Core i7 (Comet Lake-U)", "14++ nm" }, + { 6, 14, 12, -1, 142, 4, -1, -1, { "Core(TM) i5-10###U", 10 }, "Core i5 (Comet Lake-U)", "14++ nm" }, + { 6, 14, 12, -1, 142, 4, -1, -1, { "Core(TM) i3-10###U", 10 }, "Core i3 (Comet Lake-U)", "14++ nm" }, + { 6, 14, 12, -1, 142, 2, -1, -1, { "Pentium(R) Gold 6###U", 8 }, "Pentium Gold (Comet Lake-U)", "14++ nm" }, + { 6, 14, 12, -1, 142, 2, -1, -1, { "Celeron(R) 5###U", 6 }, "Celeron (Comet Lake-U)", "14++ nm" }, + { 6, 5, -1, -1, 165, -1, -1, -1, { "Xeon(R) W-10###M", 10 }, "Xeon W (Comet Lake-H)", "14++ nm" }, + { 6, 5, -1, -1, 165, -1, -1, -1, { "Core(TM) i9-10###H", 10 }, "Core i9 (Comet Lake-H)", "14++ nm" }, + { 6, 5, -1, -1, 165, -1, -1, -1, { "Core(TM) i7-10###H", 10 }, "Core i7 (Comet Lake-H)", "14++ nm" }, + { 6, 5, -1, -1, 165, -1, -1, -1, { "Core(TM) i5-10###H", 10 }, "Core i5 (Comet Lake-H)", "14++ nm" }, + + /* Goldmont CPUs (2016, Atom, 14 nm): https://en.wikipedia.org/wiki/Goldmont */ + { 6, 12, -1, -1, 92, -1, -1, -1, { "Pentium(R) J4###", 6 }, "Pentium (Apollo Lake)", "14 nm" }, + { 6, 12, -1, -1, 92, -1, -1, -1, { "Celeron(R) J3###", 6 }, "Celeron (Apollo Lake)", "14 nm" }, + { 6, 12, -1, -1, 92, -1, -1, -1, { "Pentium(R) N4###", 6 }, "Pentium (Apollo Lake)", "14 nm" }, + { 6, 12, -1, -1, 92, -1, -1, -1, { "Celeron(R) N3###", 6 }, "Celeron (Apollo Lake)", "14 nm" }, + { 6, 12, -1, -1, 92, -1, -1, -1, { "Atom(TM) E39##", 6 }, "Atom (Apollo Lake)", "14 nm" }, + { 6, 15, -1, -1, 95, -1, -1, -1, { "Atom(TM) C39##", 6 }, "Atom (Denverton)" , "14 nm" }, + + /* Goldmont Plus CPUs (2017, Atom, 14 nm): https://en.wikipedia.org/wiki/Goldmont_Plus */ + { 6, 10, -1, -1, 122, -1, -1, -1, { "Pentium(R) Silver [JN]5###", 8 }, "Pentium Silver (Gemini Lake)", "14 nm" }, + { 6, 10, -1, -1, 122, -1, -1, -1, { "Celeron(R) [JN]4###", 6 }, "Celeron (Gemini Lake)", "14 nm" }, + + /* Palm Cove CPUs (2018, 8th Core i gen, 14++ nm): https://en.wikipedia.org/wiki/Cannon_Lake_(microprocessor)*/ + { 6, 6, -1, -1, 102, 2, -1, -1, { "Core(TM) i3-8###U", 10 }, "Core i3 (Cannon Lake-U)", "14++ nm" }, /* Core i3 8121U */ + { 6, 6, -1, -1, 102, 2, -1, -1, { "Core(TM) m3-8###Y", 10 }, "Core m3 (Cannon Lake-Y)", "14++ nm" }, /* Core m3 8114Y */ + + /* Sunny Cove CPUs (2019, 10th Core i gen, 10 nm): https://en.wikipedia.org/wiki/Sunny_Cove_(microarchitecture) */ + { 6, 14, -1, -1, 126, 4, -1, -1, { "Core(TM) i7-10##NG7", 10 }, "Core i7 (Ice Lake)", "10 nm" }, + { 6, 14, -1, -1, 126, 4, -1, -1, { "Core(TM) i7-10##G7", 10 }, "Core i7 (Ice Lake)", "10 nm" }, + { 6, 14, -1, -1, 126, 4, -1, -1, { "Core(TM) i5-10##NG7", 10 }, "Core i5 (Ice Lake)", "10 nm" }, + { 6, 14, -1, -1, 126, 4, -1, -1, { "Core(TM) i5-10##G[741]", 10 }, "Core i5 (Ice Lake)", "10 nm" }, + { 6, 14, -1, -1, 126, 2, -1, -1, { "Core(TM) i3-10##G[14]", 10 }, "Core i3 (Ice Lake)", "10 nm" }, + { 6, 14, -1, -1, 126, 2, -1, -1, { "Core(TM) i3-10##NG4", 10 }, "Core i3 (Ice Lake)", "10 nm" }, + { 6, 14, -1, -1, 126, 2, -1, -1, { "Pentium(R) 68##", 4 }, "Pentium (Ice Lake)", "10 nm" }, /* Pentium 6805 */ + /* Ice Lake (server) CPUs (2021, 3rd Xeon Scalable gen, 10 nm): https://en.wikichip.org/wiki/intel/microarchitectures/ice_lake_(server) */ + { 6, 12, -1, -1, 108, -1, -1, -1, { "Xeon(R) D-[12]7##", 6 }, "Xeon D (Ice Lake-D)", "10 nm" }, + { 6, 10, -1, -1, 106, -1, -1, -1, { "Xeon(R) W-#3##", 6 }, "Xeon W (Ice Lake-W)", "10 nm" }, + { 6, 10, -1, -1, 106, -1, -1, -1, { "Xeon(R) Platinum #3##", 6 }, "Xeon Platinum (Ice Lake-SP)", "10 nm" }, + { 6, 10, -1, -1, 106, -1, -1, -1, { "Xeon(R) Gold #3##", 6 }, "Xeon Gold (Ice Lake-SP)", "10 nm" }, + { 6, 10, -1, -1, 106, -1, -1, -1, { "Xeon(R) Silver #3##", 6 }, "Xeon Silver (Ice Lake-SP)", "10 nm" }, + { 6, 10, -1, -1, 106, -1, -1, -1, { "Xeon(R) Bronze #3##", 6 }, "Xeon Bronze (Ice Lake-SP)", "10 nm" }, + + /* Tremont CPUs (2020, Atom, 10 nm): https://en.wikipedia.org/wiki/Tremont_(microarchitecture) */ + { 6, 6, -1, -1, 150, -1, -1, -1, { "Pentium(R) [JN]6###", 6 }, "Pentium (Elkhart Lake)", "10 nm" }, + { 6, 6, -1, -1, 150, -1, -1, -1, { "Celeron(R) [JN]6###", 6 }, "Celeron (Elkhart Lake)", "10 nm" }, + { 6, 6, -1, -1, 150, -1, -1, -1, { "Atom(TM) x6###", 6 }, "Atom (Elkhart Lake)", "10 nm" }, + { 6, 10, -1, -1, 138, -1, -1, -1, { "Core(TM) i5-L##G7", 12 }, "Core i5 (Lakefield)", "10 nm" }, + { 6, 10, -1, -1, 138, -1, -1, -1, { "Core(TM) i3-L##G4", 12 }, "Core i3 (Lakefield)", "10 nm" }, + { 6, 12, -1, -1, 156, -1, -1, -1, { "Pentium(R) Silver N6###", 8 }, "Pentium Silver (Jasper Lake)", "10 nm" }, + { 6, 12, -1, -1, 156, -1, -1, -1, { "Celeron(R) N[45]###", 6 }, "Celeron (Jasper Lake)", "10 nm" }, + + /* Willow Cove CPUs (2020, 11th Core i gen, 10 nm SuperFin): https://en.wikipedia.org/wiki/Willow_Cove */ + { 6, 12, -1, -1, 140, -1, -1, -1, { "Core(TM) i7-11#5G7", 12 }, "Core i7 (Tiger Lake-UP3)", "10SF" }, + { 6, 12, -1, -1, 140, -1, -1, -1, { "Core(TM) i5-11#5G7", 12 }, "Core i5 (Tiger Lake-UP3)", "10SF" }, + { 6, 12, -1, -1, 140, -1, -1, -1, { "Core(TM) i3-11#5G4", 12 }, "Core i3 (Tiger Lake-UP3)", "10SF" }, + { 6, 12, -1, -1, 140, 2, -1, -1, { "Pentium(R) Gold 7##5", 6 }, "Pentium Gold (Tiger Lake-UP3)", "10SF" }, + { 6, 12, -1, -1, 140, 2, -1, -1, { "Celeron(R) 6##5", 4 }, "Celeron (Tiger Lake-UP3)", "10SF" }, + { 6, 12, -1, -1, 140, -1, -1, -1, { "Core(TM) i7-11#0G7", 12 }, "Core i7 (Tiger Lake-UP4)", "10SF" }, + { 6, 12, -1, -1, 140, -1, -1, -1, { "Core(TM) i5-11#0G7", 12 }, "Core i5 (Tiger Lake-UP4)", "10SF" }, + { 6, 12, -1, -1, 140, -1, -1, -1, { "Core(TM) i3-11#0G4", 12 }, "Core i3 (Tiger Lake-UP4)", "10SF" }, + { 6, 12, -1, -1, 140, -1, -1, -1, { "Core(TM) i7-11###H", 10 }, "Core i7 (Tiger Lake-H35)", "10SF" }, + { 6, 12, -1, -1, 140, -1, -1, -1, { "Core(TM) i5-11###H", 10 }, "Core i5 (Tiger Lake-H35)", "10SF" }, + { 6, 13, -1, -1, 141, -1, -1, -1, { "Xeon(R) W-11###M", 10 }, "Xeon W (Tiger Lake-H)", "10SF" }, + { 6, 13, -1, -1, 141, -1, -1, -1, { "Core(TM) i9-11###H", 10 }, "Core i9 (Tiger Lake-H)", "10SF" }, + { 6, 13, -1, -1, 141, -1, -1, -1, { "Core(TM) i7-11###H", 10 }, "Core i7 (Tiger Lake-H)", "10SF" }, + { 6, 13, -1, -1, 141, -1, -1, -1, { "Core(TM) i5-11###H", 10 }, "Core i5 (Tiger Lake-H)", "10SF" }, + { 6, 13, -1, -1, 141, -1, -1, -1, { "Core(TM) i9-11###KB", 12 }, "Core i9 (Tiger Lake-B)", "10SF" }, /* i9-11900KB */ + { 6, 13, -1, -1, 141, -1, -1, -1, { "Core(TM) i7-11###B", 10 }, "Core i7 (Tiger Lake-B)", "10SF" }, /* i7-11700B */ + { 6, 13, -1, -1, 141, -1, -1, -1, { "Core(TM) i5-11###B", 10 }, "Core i5 (Tiger Lake-B)", "10SF" }, /* i5-11500B */ + { 6, 13, -1, -1, 141, -1, -1, -1, { "Core(TM) i5-11###B", 10 }, "Core i5 (Tiger Lake-B)", "10SF" }, /* i3-11100B */ + + /* Cypress Cove CPUs (2021, 11th Core i gen, 14++ nm): https://en.wikipedia.org/wiki/Sunny_Cove_(microarchitecture)#Cypress_Cove */ + { 6, 7, -1, -1, 167, -1, -1, -1, { "Core(TM) i9-11###", 8 }, "Core i9 (Rocket Lake-S)", "14++ nm" }, + { 6, 7, -1, -1, 167, -1, -1, -1, { "Core(TM) i7-11###", 8 }, "Core i7 (Rocket Lake-S)", "14++ nm" }, + { 6, 7, -1, -1, 167, -1, -1, -1, { "Core(TM) i5-11###", 8 }, "Core i5 (Rocket Lake-S)", "14++ nm" }, + { 6, 7, -1, -1, 167, -1, -1, -1, { "Xeon(R) E-23##", 6 }, "Xeon E (Rocket Lake)" , "14++ nm" }, + + /* Golden Cove (P-cores) / Gracemont (E-cores) CPUs (2021, 12th Core i gen, Intel 7): https://en.wikipedia.org/wiki/Golden_Cove */ + { 6, 7, -1, -1, 151, -1, -1, -1, { "Core(TM) i9-12###", 8 }, "Core i9 (Alder Lake-S)", "Intel 7" }, + { 6, 7, -1, -1, 151, -1, -1, -1, { "Core(TM) i7-12###", 8 }, "Core i7 (Alder Lake-S)", "Intel 7" }, + { 6, 7, -1, -1, 151, -1, -1, -1, { "Core(TM) i5-12###", 8 }, "Core i5 (Alder Lake-S)", "Intel 7" }, + { 6, 7, -1, -1, 151, -1, -1, -1, { "Core(TM) i3-12###", 8 }, "Core i3 (Alder Lake-S)", "Intel 7" }, + { 6, 7, -1, -1, 151, -1, -1, -1, { "Pentium(R) Gold G7###", 8 }, "Pentium Gold (Alder Lake-S)" , "Intel 7" }, + { 6, 7, -1, -1, 151, -1, -1, -1, { "Celeron(R) G6###", 6 }, "Celeron (Alder Lake-S)", "Intel 7" }, + { 6, 7, -1, -1, 151, -1, -1, -1, { "Core(TM) i9-12###HX", 12 }, "Core i9 (Alder Lake-HX)", "Intel 7" }, + { 6, 7, -1, -1, 151, -1, -1, -1, { "Core(TM) i7-12###HX", 12 }, "Core i7 (Alder Lake-HX)", "Intel 7" }, + { 6, 7, -1, -1, 151, -1, -1, -1, { "Core(TM) i5-12###HX", 12 }, "Core i5 (Alder Lake-HX)", "Intel 7" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i7-12##P", 10 }, "Core i7 (Alder Lake-P)", "Intel 7" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i5-12##P", 10 }, "Core i5 (Alder Lake-P)", "Intel 7" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i3-12##P", 10 }, "Core i3 (Alder Lake-P)", "Intel 7" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i7-12##U", 10 }, "Core i7 (Alder Lake-U)", "Intel 7" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i5-12##U", 10 }, "Core i5 (Alder Lake-U)", "Intel 7" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i3-12##U", 10 }, "Core i3 (Alder Lake-U)", "Intel 7" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Pentium(R) Gold 8###", 6 }, "Pentium Gold (Alder Lake-U)", "Intel 7" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Celeron(R) 7###", 4 }, "Celeron (Alder Lake-U)", "Intel 7" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i9-12###H", 10 }, "Core i9 (Alder Lake-H)", "Intel 7" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i7-12###H", 10 }, "Core i7 (Alder Lake-H)", "Intel 7" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i5-12###H", 10 }, "Core i5 (Alder Lake-H)", "Intel 7" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i7-12##UL", 12 }, "Core i7 (Alder Lake-PS)", "Intel 7" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i5-12##UL", 12 }, "Core i5 (Alder Lake-PS)", "Intel 7" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i3-12##UL", 12 }, "Core i3 (Alder Lake-PS)", "Intel 7" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Celeron(R) 7###L", 6 }, "Celeron (Alder Lake-PS)", "Intel 7" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i7-12###HL", 12 }, "Core i7 (Alder Lake-PS)", "Intel 7" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i5-12###HL", 12 }, "Core i5 (Alder Lake-PS)", "Intel 7" }, + { 6, 10, -1, -1, 154, -1, -1, -1, { "Core(TM) i3-12###HL", 12 }, "Core i3 (Alder Lake-PS)", "Intel 7" }, + /* Sapphire Rapids CPUs (2023, 4th Xeon Scalable gen, Intel 7): https://en.wikichip.org/wiki/intel/microarchitectures/sapphire_rapids */ + { 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) w9-#4##", 6 }, "Xeon w9 (Sapphire Rapids-WS)", "Intel 7" }, + { 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) w7-#4##", 6 }, "Xeon w7 (Sapphire Rapids-WS)", "Intel 7" }, + { 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) w5-#4##", 6 }, "Xeon w5 (Sapphire Rapids-WS)", "Intel 7" }, + { 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) w3-#4##", 6 }, "Xeon w3 (Sapphire Rapids-WS)", "Intel 7" }, + { 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) Max #4##", 6 }, "Xeon Max (Sapphire Rapids-HBM)", "Intel 7" }, + { 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) Platinum #4##", 6 }, "Xeon Platinum (Sapphire Rapids-SP)", "Intel 7" }, + { 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) Gold #4##", 6 }, "Xeon Gold (Sapphire Rapids-SP)", "Intel 7" }, + { 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) Silver #4##", 6 }, "Xeon Silver (Sapphire Rapids-SP)" , "Intel 7" }, + { 6, 15, -1, -1, 143, -1, -1, -1, { "Xeon(R) Bronze #4##", 6 }, "Xeon Bronze (Sapphire Rapids-SP)" , "Intel 7" }, + + /* Gracemont CPUs (2021, Atom, Intel 7): https://en.wikipedia.org/wiki/Gracemont_(microarchitecture) */ + { 6, 14, -1, -1, 190, -1, -1, -1, { "Core(TM) i3-N3##", 10 }, "Core i3 (Alder Lake-N)", "Intel 7" }, /* Core i3 N300 + Core i3 N305 */ + { 6, 14, -1, -1, 190, 4, -1, -1, { "N##", 2 }, "Intel Processor (Alder Lake-N)", "Intel 7" }, + { 6, 14, -1, -1, 190, 2, -1, -1, { "N##", 2 }, "Intel Processor (Alder Lake-N)", "Intel 7" }, /* Intel Processor N50 */ + { 6, 14, -1, -1, 190, -1, -1, -1, { "Atom(TM) x7###E", 8 }, "Atom (Alder Lake-N)", "Intel 7" }, + /* Twin Lake CPUs (2025, Atom, Intel 7): https://en.wikichip.org/wiki/intel/microarchitectures/twin_lake */ + { 6, 14, -1, -1, 190, 8, -1, -1, { "Core(TM) 3 N#5#", 8 }, "Core 3 (Twin Lake-N)", "Intel 7" }, /* Core 3 N350 + Core 3 N355 */ + { 6, 14, -1, -1, 190, 4, -1, -1, { "N#5#", 4 }, "Intel Processor (Twin Lake-N)", "Intel 7" }, /* Intel Processor N150 + Intel Processor N150 */ + + /* Raptor Cove (P-cores) / Gracemont (E-cores) CPUs (2022, 13th Core i gen, Intel 7): https://en.wikipedia.org/wiki/Golden_Cove#Raptor_Cove */ + { 6, 15, -1, -1, 191, -1, -1, -1, { "Core(TM) i5-13###", 8 }, "Core i5 (Raptor Lake-S)", "Intel 7" }, /* "Golden Cove" cores */ + { 6, 15, -1, -1, 191, -1, -1, -1, { "Core(TM) i3-13###", 8 }, "Core i3 (Raptor Lake-S)", "Intel 7" }, /* "Golden Cove" cores */ + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i9-13###", 8 }, "Core i9 (Raptor Lake-S)", "Intel 7" }, + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i7-13###", 8 }, "Core i7 (Raptor Lake-S)", "Intel 7" }, + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i5-13###", 8 }, "Core i5 (Raptor Lake-S)", "Intel 7" }, + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i3-13###", 8 }, "Core i3 (Raptor Lake-S)", "Intel 7" }, + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i9-13###HX", 12 }, "Core i9 (Raptor Lake-HX)", "Intel 7" }, + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i7-13###HX", 12 }, "Core i7 (Raptor Lake-HX)", "Intel 7" }, + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i5-13###HX", 12 }, "Core i5 (Raptor Lake-HX)", "Intel 7" }, + { 6, 10, 2, -1, 186, -1, -1, -1, { "Core(TM) i7-13###P", 10 }, "Core i7 (Raptor Lake-P)", "Intel 7" }, + { 6, 10, 2, -1, 186, -1, -1, -1, { "Core(TM) i5-13###P", 10 }, "Core i5 (Raptor Lake-P)", "Intel 7" }, + { 6, 10, 3, -1, 186, -1, -1, -1, { "Core(TM) i7-13###U", 10 }, "Core i7 (Raptor Lake-U)", "Intel 7" }, + { 6, 10, 3, -1, 186, -1, -1, -1, { "Core(TM) i5-13###U", 10 }, "Core i5 (Raptor Lake-U)", "Intel 7" }, + { 6, 10, 3, -1, 186, -1, -1, -1, { "Core(TM) i3-13###U", 10 }, "Core i3 (Raptor Lake-U)", "Intel 7" }, + { 6, 10, 3, -1, 186, -1, -1, -1, { "U300", 4 }, "Intel Processor (Raptor Lake-U)", "Intel 7" }, /* Intel Processor U300 */ + { 6, 10, -1, -1, 186, -1, -1, -1, { "Core(TM) i9-13###H", 10 }, "Core i9 (Raptor Lake-H)", "Intel 7" }, + { 6, 10, -1, -1, 186, -1, -1, -1, { "Core(TM) i7-13###H", 10 }, "Core i7 (Raptor Lake-H)", "Intel 7" }, + { 6, 10, -1, -1, 186, -1, -1, -1, { "Core(TM) i5-13###H", 10 }, "Core i5 (Raptor Lake-H)", "Intel 7" }, + /* Emerald Rapids CPUs (2023, 5th Xeon Scalable gen, Intel 7): https://en.wikichip.org/wiki/intel/microarchitectures/emerald_rapids */ + { 6, 15, -1, -1, 207, -1, -1, -1, { "Xeon(R) Platinum #5##", 6 }, "Xeon Platinum (Emerald Rapids-SP)", "Intel 7" }, /* Xeon Platinum (8500) */ + { 6, 15, -1, -1, 207, -1, -1, -1, { "Xeon(R) Gold #5##", 6 }, "Xeon Gold (Emerald Rapids-SP)", "Intel 7" }, /* Xeon Gold (5500 and 6500) */ + { 6, 15, -1, -1, 207, -1, -1, -1, { "Xeon(R) Silver #5##", 6 }, "Xeon Silver (Emerald Rapids-SP)", "Intel 7" }, /* Xeon Silver (4500) */ + { 6, 15, -1, -1, 207, -1, -1, -1, { "Xeon(R) Bronze #5##", 6 }, "Xeon Bronze (Emerald Rapids-SP)", "Intel 7" }, /* Xeon Bronze (3500) */ + /* Raptor Lake Refresh CPUs (2023, 14th Core i gen, Intel 7): https://en.wikipedia.org/wiki/Raptor_Lake#List_of_14th_generation_Raptor_Lake_processors */ + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i9-14###", 8 }, "Core i9 (Raptor Lake-S)" , "Intel 7" }, + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i7-14###", 8 }, "Core i7 (Raptor Lake-S)" , "Intel 7" }, + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i5-14###", 8 }, "Core i5 (Raptor Lake-S)" , "Intel 7" }, + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i3-14###", 8 }, "Core i3 (Raptor Lake-S)" , "Intel 7" }, + { 6, 7, -1, -1, 183, 2, -1, -1, { "300", 2 }, "Intel Processor (Raptor Lake-S)", "Intel 7" }, /* Intel Processor 300 + Intel Processor 300T */ + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i9-14###HX", 12 }, "Core i9 (Raptor Lake-HX)", "Intel 7" }, + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i7-14###HX", 12 }, "Core i7 (Raptor Lake-HX)", "Intel 7" }, + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) i5-14###HX", 12 }, "Core i5 (Raptor Lake-HX)", "Intel 7" }, + { 6, 7, -1, -1, 183, -1, -1, -1, { "Xeon(R) E-24##", 6 }, "Xeon E (Raptor Lake)", "Intel 7" }, + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) 7 1##U", 8 }, "Core 7 (Raptor Lake-U)", "Intel 7" }, /* Core 7 150U */ + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) 5 1##U", 8 }, "Core 5 (Raptor Lake-U)", "Intel 7" }, /* Core 5 120U */ + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) 3 1##U", 8 }, "Core 3 (Raptor Lake-U)", "Intel 7" }, /* Core 3 100U */ + /* Raptor Lake Re-refresh CPUs (2025, Core Series 2, Intel 7): https://en.wikipedia.org/wiki/Raptor_Lake#List_of_Core_Series_2_processors */ + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) 7 2##U", 8 }, "Core 7 (Raptor Lake-U)", "Intel 7" }, /* Core 7 250U */ + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) 5 2##U", 8 }, "Core 5 (Raptor Lake-U)", "Intel 7" }, /* Core 5 220U */ + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) 9 2##H", 8 }, "Core 9 (Raptor Lake-H)", "Intel 7" }, /* Core 9 270H */ + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) 7 2##H", 8 }, "Core 7 (Raptor Lake-H)", "Intel 7" }, /* Core 7 240H + Core 7 250H */ + { 6, 7, -1, -1, 183, -1, -1, -1, { "Core(TM) 5 2##H", 8 }, "Core 5 (Raptor Lake-H)", "Intel 7" }, /* Core 5 210H + Core 5 220H */ + + /* Redwood Cove (P-cores) / Crestmont (E-cores) CPUs (2023, Core Ultra Series 1, Intel 4): https://en.wikipedia.org/wiki/Meteor_Lake */ + { 6, 10, -1, -1, 170, -1, -1, -1, { "Core(TM) Ultra 9 1##H", 10 }, "Core Ultra 9 (Meteor Lake-H)", "Intel 4" }, + { 6, 10, -1, -1, 170, -1, -1, -1, { "Core(TM) Ultra 7 1##H", 10 }, "Core Ultra 7 (Meteor Lake-H)", "Intel 4" }, + { 6, 10, -1, -1, 170, -1, -1, -1, { "Core(TM) Ultra 5 1##H", 10 }, "Core Ultra 5 (Meteor Lake-H)", "Intel 4" }, + { 6, 10, -1, -1, 170, -1, -1, -1, { "Core(TM) Ultra 7 1##U", 10 }, "Core Ultra 7 (Meteor Lake-U)", "Intel 4" }, + { 6, 10, -1, -1, 170, -1, -1, -1, { "Core(TM) Ultra 5 1##U", 10 }, "Core Ultra 5 (Meteor Lake-U)", "Intel 4" }, + /* Granite Rapids CPUs (2024, 6th Xeon Scalable gen, Intel 7): https://en.wikipedia.org/wiki/Granite_Rapids */ + { 6, 13, -1, -1, 173, -1, -1, -1, { "Xeon(R) 6[57]##P", 6 }, "Xeon 6 (Granite Rapids-SP)", "Intel 3" }, + //{ 6, ??, -1, -1, ???, -1, -1, -1, { "Xeon(R) 6[57]##P", 6 }, "Xeon 6 (Granite Rapids-AP)", "Intel 3" }, + //{ 6, 14, -1, -1, 174, -1, -1, -1, { "Xeon(R) ????", 4 }, "Xeon ??? (Granite Rapids-D)", "Intel 3" }, + + /* Lion Cove (P-cores) / Skymont (E-cores) CPUs (2024, Core Ultra Series 2, TSMC N3B): https://en.wikipedia.org/wiki/Arrow_Lake_(microprocessor) */ + { 6, 6, -1, -1, 198, -1, -1, -1, { "Core(TM) Ultra 9 2##", 8 }, "Core Ultra 9 (Arrow Lake-S)", "TSMC N3B" }, + { 6, 6, -1, -1, 198, -1, -1, -1, { "Core(TM) Ultra 7 2##", 8 }, "Core Ultra 7 (Arrow Lake-S)", "TSMC N3B" }, + { 6, 6, -1, -1, 198, -1, -1, -1, { "Core(TM) Ultra 5 2##", 8 }, "Core Ultra 5 (Arrow Lake-S)", "TSMC N3B" }, + { 6, 6, -1, -1, 181, -1, -1, -1, { "Core(TM) Ultra 7 2##U", 10 }, "Core Ultra 7 (Arrow Lake-U)", "TSMC N3B" }, /* Core Ultra 7 255U + Core Ultra 7 265U */ + { 6, 6, -1, -1, 181, -1, -1, -1, { "Core(TM) Ultra 5 2##U", 10 }, "Core Ultra 5 (Arrow Lake-U)", "TSMC N3B" }, /* Core Ultra 5 225U + Core Ultra 5 235U */ + { 6, 6, -1, -1, 197, -1, -1, -1, { "Core(TM) Ultra 9 2##H", 10 }, "Core Ultra 9 (Arrow Lake-H)", "TSMC N3B" }, /* Core Ultra 9 285H */ + { 6, 6, -1, -1, 197, -1, -1, -1, { "Core(TM) Ultra 7 2##H", 10 }, "Core Ultra 7 (Arrow Lake-H)", "TSMC N3B" }, /* Core Ultra 7 255H + Core Ultra 7 265H */ + { 6, 6, -1, -1, 197, -1, -1, -1, { "Core(TM) Ultra 5 2##H", 10 }, "Core Ultra 5 (Arrow Lake-H)", "TSMC N3B" }, /* Core Ultra 5 225H + Core Ultra 5 235H */ + { 6, 6, -1, -1, 197, -1, -1, -1, { "Core(TM) Ultra 9 2##HX", 12 }, "Core Ultra 9 (Arrow Lake-HX)", "TSMC N3B" }, /* Core Ultra 9 275HX + Core Ultra 9 285HX */ + { 6, 6, -1, -1, 197, -1, -1, -1, { "Core(TM) Ultra 7 2##HX", 12 }, "Core Ultra 7 (Arrow Lake-HX)", "TSMC N3B" }, /* Core Ultra 7 255HX + Core Ultra 7 265HX */ + { 6, 6, -1, -1, 197, -1, -1, -1, { "Core(TM) Ultra 5 2##HX", 12 }, "Core Ultra 5 (Arrow Lake-HX)", "TSMC N3B" }, /* Core Ultra 5 235HX + Core Ultra 5 245HX */ + { 6, 13, -1, -1, 189, -1, -1, -1, { "Core(TM) Ultra 9 2##V", 10 }, "Core Ultra 9 (Lunar Lake-V)", "TSMC N3B" }, + { 6, 13, -1, -1, 189, -1, -1, -1, { "Core(TM) Ultra 7 2##V", 10 }, "Core Ultra 7 (Lunar Lake-V)", "TSMC N3B" }, + { 6, 13, -1, -1, 189, -1, -1, -1, { "Core(TM) Ultra 5 2##V", 10 }, "Core Ultra 5 (Lunar Lake-V)", "TSMC N3B" }, + + /* Cougar Cove (P-cores) / Darkmont (E-cores and LP E-cores) CPUs (2025, Core Ultra Series 3, Intel 18A): https://en.wikipedia.org/wiki/Panther_Lake_(microprocessor) */ + // TBA +// F M S EF EM #cores L2$ L3$ Pattern Codename Technology + + + /* Itaniums */ + { 7, -1, -1, -1, -1, 1, -1, -1, { "", 0 }, "Itanium", UNKN_STR }, + { 15, -1, -1, 16, -1, 1, -1, -1, { "", 0 }, "Itanium 2", UNKN_STR }, +}; + +// https://github.com/anrieff/libcpuid/blob/2e4456ae0165db3155da2e8fba92afd5c090ca1b/libcpuid/recog_amd.c +/* + * Copyright 2008 Veselin Georgiev, + * anrieffNOSPAM @ mgail_DOT.com (convert to gmail) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /* + * Useful links: + * - List of AMD CPU microarchitectures: https://en.wikipedia.org/wiki/List_of_AMD_CPU_microarchitectures + * - List of AMD Athlon processors: https://en.wikipedia.org/wiki/List_of_AMD_Athlon_processors#Desktop_processors + * - List of AMD Duron processors: https://en.wikipedia.org/wiki/List_of_AMD_Duron_processors + * - List of AMD Sempron processors: https://en.wikipedia.org/wiki/List_of_AMD_Sempron_processors + * - List of AMD Turion processors: https://en.wikipedia.org/wiki/List_of_AMD_Turion_processors + * - List of AMD Opteron processors: https://en.wikipedia.org/wiki/List_of_AMD_Opteron_processors + * - List of AMD Phenom processors: https://en.wikipedia.org/wiki/List_of_AMD_Phenom_processors + * - List of AMD FX processors: https://en.wikipedia.org/wiki/List_of_AMD_FX_processors + * - List of AMD processors with 3D graphics: https://en.wikipedia.org/wiki/List_of_AMD_processors_with_3D_graphics + * - List of AMD Ryzen processors: https://en.wikipedia.org/wiki/List_of_AMD_Ryzen_processors + * - List of AMD Epyc processors: https://en.wikipedia.org/wiki/Epyc#List_of_Epyc_processors + * - Processor Specifications: https://www.amd.com/en/products/specifications/processors.html + */ +const struct match_entry_t cpudb_amd[] = { +// F M S EF EM #cores L2$ L3$ Pattern Codename Technology + { -1, -1, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown AMD CPU", UNKN_STR }, + + /* 486 and the likes */ + { 4, -1, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown 486", UNKN_STR }, + { 4, 3, -1, -1, -1, 1, -1, -1, { "", 0 }, "AMD 486DX2", UNKN_STR }, + { 4, 7, -1, -1, -1, 1, -1, -1, { "", 0 }, "AMD 486DX2WB", UNKN_STR }, + { 4, 8, -1, -1, -1, 1, -1, -1, { "", 0 }, "AMD 486DX4", UNKN_STR }, + { 4, 9, -1, -1, -1, 1, -1, -1, { "", 0 }, "AMD 486DX4WB", UNKN_STR }, + + /* Pentia clones */ + { 5, -1, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown K5", UNKN_STR }, + { 5, 0, -1, -1, -1, 1, -1, -1, { "", 0 }, "K5 (SSA/5)", UNKN_STR }, + { 5, 1, -1, -1, -1, 1, -1, -1, { "K5(tm)", 2 }, "K5 (5k86)", "350 nm" }, + { 5, 2, -1, -1, -1, 1, -1, -1, { "K5(tm)", 2 }, "K5 (5k86)", "350 nm" }, + { 5, 3, -1, -1, -1, 1, -1, -1, { "K5(tm)", 2 }, "K5 (5k86)", "350 nm" }, + + /* K6 Architecture */ + { 5, -1, -1, -1, -1, 1, -1, -1, { "", 0 }, "Unknown K6", UNKN_STR }, + { 5, 6, -1, -1, -1, 1, -1, -1, { "K6", 2 }, "K6", "350 nm" }, + { 5, 7, -1, -1, -1, 1, -1, -1, { "K6", 2 }, "K6 (Little Foot)", "250 nm" }, + { 5, 8, 0, -1, -1, 1, -1, -1, { "K6(tm)", 2 }, "K6-2 (Chomper)", "250 nm" }, + { 5, 8, 12, -1, -1, 1, -1, -1, { "K6(tm)", 2 }, "K6-2 (Chomper Extended)", "250 nm" }, + { 5, 9, -1, -1, -1, 1, -1, -1, { "K6(tm)", 2 }, "K6-III (Sharptooth)", "250 nm" }, + { 5, 13, -1, -1, -1, 1, -1, -1, { "K6(tm)", 2 }, "K6-2+", "180 nm" }, + { 5, 13, -1, -1, -1, 1, -1, -1, { "K6(tm)-III ", 4 }, "K6-III+", "180 nm" }, + + /* K7 Architecture */ + { 6, -1, -1, 15, -1, 1, -1, -1, { "", 0 }, "Unknown K7", UNKN_STR }, + + { 6, 1, -1, -1, -1, 1, -1, -1, { "K7(tm)", 0 }, "Athlon (Argon)", "250 nm" }, + + { 6, 2, -1, -1, -1, 1, -1, -1, { "Athlon(tm)", 0 }, "Athlon (Pluto/Orion)", "180 nm" }, + + { 6, 3, -1, -1, -1, 1, -1, -1, { "Duron(tm)", 2 }, "Duron (Spitfire)", "180 nm" }, + { 6, 3, -1, -1, -1, 1, -1, -1, { "Duron(tm) M", 4 }, "Mobile Duron (Spitfire)", "180 nm" }, + + { 6, 4, -1, -1, -1, 1, -1, -1, { "Athlon(tm)", 2 }, "Athlon (ThunderBird)", "180 nm" }, + + { 6, 6, -1, -1, -1, 1, -1, -1, { "Athlon XP", 4 }, "Athlon (Palomino)", "180 nm" }, + { 6, 6, -1, -1, -1, 1, -1, -1, { "Athlon(tm) MP", 4 }, "Athlon MP (Palomino)", "180 nm" }, + { 6, 6, -1, -1, -1, 1, -1, -1, { "Duron(tm)", 2 }, "Duron (Palomino)", "180 nm" }, + + { 6, 7, -1, -1, -1, 1, -1, -1, { "Duron(tm)", 2 }, "Duron (Morgan)", "180 nm" }, + { 6, 7, -1, -1, -1, 1, -1, -1, { "Duron(tm) M", 4 }, "Mobile Duron (Camaro)", "180 nm" }, + + { 6, 8, -1, -1, -1, 1, -1, -1, { "Athlon", 2 }, "Athlon XP (Thoroughbred)", "130 nm" }, + { 6, 8, -1, -1, -1, 1, -1, -1, { "Athlon(tm) XP", 4 }, "Athlon XP (Thoroughbred)", "130 nm" }, + { 6, 8, -1, -1, -1, 1, -1, -1, { "Duron(tm)", 2 }, "Duron (Applebred)", "130 nm" }, + { 6, 8, -1, -1, -1, 1, -1, -1, { "Sempron(tm)", 2 }, "Sempron (Thoroughbred)", "130 nm" }, + { 6, 8, -1, -1, -1, 1, 128, -1, { "Sempron(tm)", 2 }, "Sempron (Thoroughbred)", "130 nm" }, + { 6, 8, -1, -1, -1, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron (Thoroughbred)", "130 nm" }, + { 6, 8, -1, -1, -1, 1, -1, -1, { "Athlon(tm) MP", 4 }, "Athlon MP (Thoroughbred)", "130 nm" }, + { 6, 8, -1, -1, -1, 1, -1, -1, { "Athlon(tm) XP-M", 6 }, "Mobile Athlon (Thoroughbred)", "130 nm" }, + + { 6, 10, -1, -1, -1, 1, 512, -1, { "Athlon(tm) XP", 4 }, "Athlon XP (Barton)", "130 nm" }, + { 6, 10, -1, -1, -1, 1, 512, -1, { "Sempron(tm)", 2 }, "Sempron (Barton)", "130 nm" }, + { 6, 10, -1, -1, -1, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron (Thorton)", "130 nm" }, + { 6, 10, -1, -1, -1, 1, 256, -1, { "Athlon(tm) XP", 4 }, "Athlon XP (Thorton)", "130 nm" }, + { 6, 10, -1, -1, -1, 1, -1, -1, { "Athlon(tm) MP", 4 }, "Athlon MP (Barton)", "130 nm" }, + { 6, 10, -1, -1, -1, 1, -1, -1, { "Athlon(tm) XP-M", 6 }, "Mobile Athlon (Barton)", "130 nm" }, + + /* K8 Architecture */ + { 15, -1, -1, 15, -1, 1, -1, -1, { "", 0 }, "Unknown K8", UNKN_STR }, + { 15, -1, -1, 16, -1, 1, -1, -1, { "", 0 }, "Unknown K9", UNKN_STR }, + { 15, -1, -1, 15, -1, 1, -1, -1, { "", 0 }, "Unknown A64", UNKN_STR }, + { 15, -1, -1, 15, -1, 1, -1, -1, { "Opteron(tm)", 2 }, "Opteron", UNKN_STR }, + { 15, -1, -1, 15, -1, 2, -1, -1, { "Dual Core AMD Opteron", 8 }, "Opteron (Dual Core)", UNKN_STR }, + { 15, 1, -1, 15, 65, 2, -1, -1, { "Opteron(tm) 22##", 6 }, "Opteron (Santa Rosa)", "90 nm" }, + { 15, 3, -1, 15, -1, 1, -1, -1, { "Opteron(tm)", 2 }, "Opteron", UNKN_STR }, + { 15, 3, -1, 15, -1, 2, -1, -1, { "Dual Core AMD Opteron", 8 }, "Opteron (Dual Core)", UNKN_STR }, + { 15, 5, -1, 15, 5, -1, -1, -1, { "Opteron(tm) [128]##", 4 }, "Opteron (SledgeHammer)", "130 nm" }, + { 15, -1, -1, 15, -1, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (512K)", UNKN_STR }, + { 15, -1, -1, 15, -1, 1, 1024, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (1024K)", UNKN_STR }, + { 15, -1, -1, 15, -1, 1, -1, -1, { "Athlon(tm) FX", 4 }, "Athlon FX", UNKN_STR }, + { 15, -1, -1, 15, -1, 1, -1, -1, { "Athlon(tm) 64 FX", 6 }, "Athlon 64 FX", UNKN_STR }, + { 15, 3, -1, 15, 35, 2, -1, -1, { "Athlon(tm) 64 FX", 6 }, "Athlon 64 FX X2 (Toledo)", "90 nm" }, + { 15, -1, -1, 15, -1, 2, 512, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (512K)", UNKN_STR }, + { 15, -1, -1, 15, -1, 2, 1024, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (1024K)", UNKN_STR }, + { 15, -1, -1, 15, -1, 1, 512, -1, { "Turion(tm) 64", 4 }, "Turion 64 (512K)", UNKN_STR }, + { 15, -1, -1, 15, -1, 1, 1024, -1, { "Turion(tm) 64", 4 }, "Turion 64 (1024K)", UNKN_STR }, + { 15, -1, -1, 15, -1, 2, 512, -1, { "Turion(tm) X2", 4 }, "Turion 64 X2 (512K)", UNKN_STR }, + { 15, -1, -1, 15, -1, 2, 1024, -1, { "Turion(tm) X2", 4 }, "Turion 64 X2 (1024K)", UNKN_STR }, + { 15, -1, -1, 15, -1, 1, 128, -1, { "Sempron(tm)", 2 }, "A64 Sempron (128K)", UNKN_STR }, + { 15, -1, -1, 15, -1, 1, 256, -1, { "Sempron(tm)", 2 }, "A64 Sempron (256K)", UNKN_STR }, + { 15, -1, -1, 15, -1, 1, 512, -1, { "Sempron(tm)", 2 }, "A64 Sempron (512K)", UNKN_STR }, + { 15, -1, -1, 15, 0x4f, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (Orleans/512K)", "90 nm" }, + { 15, -1, -1, 15, 0x5f, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (Orleans/512K)", "90 nm" }, + { 15, -1, -1, 15, 0x2f, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (Venice/512K)", "90 nm" }, + { 15, -1, -1, 15, 0x2c, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (Venice/512K)", "90 nm" }, + { 15, -1, -1, 15, 0x1f, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (Winchester/512K)", "90 nm" }, + { 15, -1, -1, 15, 0x0c, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (Newcastle/512K)", "130 nm" }, + { 15, -1, -1, 15, 0x27, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (San Diego/512K)", "90 nm" }, + { 15, -1, -1, 15, 0x37, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (San Diego/512K)", "90 nm" }, + { 15, -1, -1, 15, 0x04, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (ClawHammer/512K)", "130 nm" }, + + { 15, -1, -1, 15, 0x5f, 1, 1024, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (Orleans/1024K)", "90 nm" }, + { 15, -1, -1, 15, 0x27, 1, 1024, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (San Diego/1024K)", "90 nm" }, + { 15, -1, -1, 15, 0x04, 1, 1024, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (ClawHammer/1024K)", "130 nm" }, + + { 15, -1, -1, 15, 0x4b, 2, 256, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (Windsor/256K)", "90 nm" }, + + { 15, -1, -1, 15, 0x23, 2, 512, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (Toledo/512K)", "90 nm" }, + { 15, -1, -1, 15, 0x4b, 2, 512, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (Windsor/512K)", "90 nm" }, + { 15, -1, -1, 15, 0x43, 2, 512, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (Windsor/512K)", "90 nm" }, + { 15, -1, -1, 15, 0x6b, 2, 512, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (Brisbane/512K)", "65 nm" }, + { 15, -1, -1, 15, 0x2b, 2, 512, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (Manchester/512K)", "90 nm" }, + + { 15, -1, -1, 15, 0x23, 2, 1024, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (Toledo/1024K)", "90 nm" }, + { 15, -1, -1, 15, 0x43, 2, 1024, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon 64 X2 (Windsor/1024K)", "90 nm" }, + + { 15, -1, -1, 15, 0x08, 1, 128, -1, { "Mobile AMD Sempron(tm)", 6 }, "Mobile Sempron 64 (Dublin/128K)", "130 nm" }, + { 15, -1, -1, 15, 0x08, 1, 256, -1, { "Mobile AMD Sempron(tm)", 6 }, "Mobile Sempron 64 (Dublin/256K)", "130 nm" }, + { 15, -1, -1, 15, 0x0c, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Paris)", "130 nm" }, + { 15, -1, -1, 15, 0x1c, 1, 128, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Palermo/128K)", "90 nm" }, + { 15, -1, -1, 15, 0x1c, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Palermo/256K)", "90 nm" }, + { 15, -1, -1, 15, 0x1c, 1, 128, -1, { "Mobile AMD Sempron(tm)", 6 }, "Mobile Sempron 64 (Sonora/128K)", "90 nm" }, + { 15, -1, -1, 15, 0x1c, 1, 256, -1, { "Mobile AMD Sempron(tm)", 6 }, "Mobile Sempron 64 (Sonora/256K)", "90 nm" }, + { 15, -1, -1, 15, 0x2c, 1, 128, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Palermo/128K)", "90 nm" }, + { 15, -1, -1, 15, 0x2c, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Palermo/256K)", "90 nm" }, + { 15, -1, -1, 15, 0x2c, 1, 128, -1, { "Mobile AMD Sempron(tm)", 6 }, "Mobile Sempron 64 (Albany/128K)", "90 nm" }, + { 15, -1, -1, 15, 0x2c, 1, 256, -1, { "Mobile AMD Sempron(tm)", 6 }, "Mobile Sempron 64 (Albany/256K)", "90 nm" }, + { 15, -1, -1, 15, 0x2f, 1, 128, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Palermo/128K)", "90 nm" }, + { 15, -1, -1, 15, 0x2f, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Palermo/256K)", "90 nm" }, + { 15, -1, -1, 15, 0x4f, 1, 128, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Manila/128K)", "90 nm" }, + { 15, -1, -1, 15, 0x4f, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Manila/256K)", "90 nm" }, + { 15, -1, -1, 15, 0x5f, 1, 128, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Manila/128K)", "90 nm" }, + { 15, -1, -1, 15, 0x5f, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Manila/256K)", "90 nm" }, + { 15, -1, -1, 15, 0x6b, 2, 256, -1, { "Sempron(tm)", 2 }, "Sempron 64 Dual (Sherman/256K)", "65 nm" }, + { 15, -1, -1, 15, 0x6b, 2, 512, -1, { "Sempron(tm)", 2 }, "Sempron 64 Dual (Sherman/512K)", "65 nm" }, + { 15, -1, -1, 15, 0x7c, 1, 512, -1, { "Athlon(tm) 64", 4 }, "Athlon 64 (Sherman/512K)", "65 nm" }, + { 15, -1, -1, 15, 0x7f, 1, 256, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Sparta/256K)", "65 nm" }, + { 15, -1, -1, 15, 0x7f, 1, 512, -1, { "Sempron(tm)", 2 }, "Sempron 64 (Sparta/512K)", "65 nm" }, + { 15, -1, -1, 15, 0x4c, 1, 256, -1, { "Mobile AMD Sempron(tm)", 6 }, "Mobile Sempron 64 (Keene/256K)", "90 nm" }, + { 15, -1, -1, 15, 0x4c, 1, 512, -1, { "Mobile AMD Sempron(tm)", 6 }, "Mobile Sempron 64 (Keene/512K)", "90 nm" }, + + { 15, -1, -1, 15, 0x24, 1, 512, -1, { "Turion(tm) 64", 4 }, "Turion 64 (Lancaster/512K)", "90 nm" }, + { 15, -1, -1, 15, 0x24, 1, 1024, -1, { "Turion(tm) 64", 4 }, "Turion 64 (Lancaster/1024K)", "90 nm" }, + { 15, -1, -1, 15, 0x48, 2, 256, -1, { "Turion(tm) X2", 4 }, "Turion X2 (Taylor)", "90 nm" }, + { 15, -1, -1, 15, 0x48, 2, 512, -1, { "Turion(tm) X2", 4 }, "Turion X2 (Trinidad)", "90 nm" }, + { 15, -1, -1, 15, 0x4c, 1, 512, -1, { "Turion(tm) 64", 4 }, "Turion 64 (Richmond)", "90 nm" }, + { 15, -1, -1, 15, 0x68, 2, 256, -1, { "Turion(tm) X2", 4 }, "Turion X2 (Tyler/256K)", "65 nm" }, + { 15, -1, -1, 15, 0x68, 2, 512, -1, { "Turion(tm) X2", 4 }, "Turion X2 (Tyler/512K)", "65 nm" }, + { 15, -1, -1, 17, 3, 2, 512, -1, { "Turion(tm) X2", 4 }, "Turion X2 (Griffin/512K)", "65 nm" }, + { 15, -1, -1, 17, 3, 2, 1024, -1, { "Turion(tm) X2", 4 }, "Turion X2 (Griffin/1024K)", "65 nm" }, + + /* K10 Architecture (2007) */ + { 15, 2, -1, 16, -1, 3, -1, -1, { "Phenom(tm)", 2 }, "Phenom X3 (Toliman)", "65 nm" }, + { 15, 2, -1, 16, -1, 4, -1, -1, { "Phenom(tm)", 2 }, "Phenom X4 (Agena)", "65 nm" }, + { 15, 2, -1, 16, -1, 3, 512, -1, { "Phenom(tm)", 2 }, "Phenom X3 (Toliman/256K)", "65 nm" }, + { 15, 2, -1, 16, -1, 3, 512, -1, { "Phenom(tm)", 2 }, "Phenom X3 (Toliman/512K)", "65 nm" }, + { 15, 2, -1, 16, -1, 4, 128, -1, { "Phenom(tm)", 2 }, "Phenom X4 (Agena/128K)", "65 nm" }, + { 15, 2, -1, 16, -1, 4, 256, -1, { "Phenom(tm)", 2 }, "Phenom X4 (Agena/256K)", "65 nm" }, + { 15, 2, -1, 16, -1, 4, 512, -1, { "Phenom(tm)", 2 }, "Phenom X4 (Agena/512K)", "65 nm" }, + { 15, 2, -1, 16, -1, 2, 512, -1, { "Athlon(tm) 64 X2", 6 }, "Athlon X2 (Kuma)", "65 nm" }, + /* Phenom II derivates: */ + { 15, 4, -1, 16, -1, 1, 1024, -1, { "Sempron(tm)", 2 }, "Sempron (Sargas)", "45 nm" }, + { 15, 4, -1, 16, -1, 2, 512, -1, { "Phenom(tm) II", 4 }, "Phenom II X2 (Callisto)", "45 nm" }, + { 15, 4, -1, 16, -1, 3, 512, -1, { "Phenom(tm) II", 4 }, "Phenom II X3 (Heka)", "45 nm" }, + { 15, 4, -1, 16, 4, 4, 512, -1, { "Phenom(tm) II", 4 }, "Phenom II X4 (Deneb)", "45 nm" }, + { 15, 5, -1, 16, 5, 4, 512, -1, { "Phenom(tm) II", 4 }, "Phenom II X4 (Deneb)", "45 nm" }, + { 15, 4, -1, 16, 10, 4, 512, -1, { "Phenom(tm) II", 4 }, "Phenom II X4 (Zosma)", "45 nm" }, + { 15, 4, -1, 16, 10, 6, 512, -1, { "Phenom(tm) II", 4 }, "Phenom II X6 (Thuban)", "45 nm" }, + /* Athlon II derivates: */ + { 15, 6, -1, 16, 6, 2, 512, -1, { "Athlon(tm) II", 4 }, "Athlon II (Champlain)", "45 nm" }, + { 15, 6, -1, 16, 6, 2, 512, -1, { "Athlon(tm) II X2", 6 }, "Athlon II X2 (Regor)", "45 nm" }, + { 15, 6, -1, 16, 6, 2, 1024, -1, { "Athlon(tm) II X2", 6 }, "Athlon II X2 (Regor)", "45 nm" }, + { 15, 5, -1, 16, 5, 3, 512, -1, { "Athlon(tm) II X3", 6 }, "Athlon II X3 (Rana)", "45 nm" }, + { 15, 5, -1, 16, 5, 4, 512, -1, { "Athlon(tm) X4", 4 }, "Athlon II X4 (Propus)", "45 nm" }, + { 15, 5, -1, 16, 5, 4, 512, -1, { "Athlon(tm) II X4", 6 }, "Athlon II X4 (Propus)", "45 nm" }, + /* Opteron derivates: */ + { 15, 2, -1, 16, 2, -1, -1, -1, { "Opteron(tm) [28]3##", 4 }, "Opteron (Barcelona)", "45 nm" }, + { 15, 4, -1, 16, 4, -1, -1, -1, { "Opteron(tm) [28]3##", 4 }, "Opteron (Shanghai)", "45 nm" }, + { 15, 8, -1, 16, 8, -1, -1, -1, { "Opteron(tm) [28]4##", 4 }, "Opteron (Istanbul)", "45 nm" }, + { 15, 8, -1, 16, 8, -1, -1, -1, { "Opteron(tm) 41##", 4 }, "Opteron (Lisbon)", "45 nm" }, + { 15, 9, -1, 16, 9, 8, -1, -1, { "Opteron(tm) 64##", 4 }, "Opteron (Magny-Cours)", "45 nm" }, + + /* Llano APUs (2011): */ + { 15, 1, -1, 18, 1, 4, -1, -1, { "Athlon(tm) II X4 6##", 6 }, "Athlon II X4 (Llano)", "GF 32SHP" }, + { 15, 1, -1, 18, 1, 2, -1, -1, { "Athlon(tm) II X2 2##", 6 }, "Athlon II X2 (Llano)", "GF 32SHP" }, + { 15, 1, -1, 18, 1, 2, -1, -1, { "Sempron(tm) X2 1##", 6 }, "Sempron X2 (Llano)", "GF 32SHP" }, + { 15, 1, -1, 18, 1, -1, -1, -1, { "E2-3###", 4 }, "E-Series (Llano)", "GF 32SHP" }, + { 15, 1, -1, 18, 1, -1, -1, -1, { "A[468]-3###", 4 }, "A-Series (Llano)", "GF 32SHP" }, + + /* Family 14h: Bobcat Architecture (2011) */ + { 15, 1, -1, 20, -1, -1, -1, -1, { "C-[356]#", 4 }, "C-Series (Ontario)", "TSMC N40" }, + { 15, 1, -1, 20, -1, -1, -1, -1, { "E-[234]##", 4 }, "E-Series (Zacate)", "TSMC N40" }, + { 15, 1, -1, 20, -1, -1, -1, -1, { "G-T##[LRNE]", 6 }, "G-Series (Zacate)", "TSMC N40" }, + { 15, 1, -1, 20, -1, -1, -1, -1, { "Z-##", 4 }, "Z-Series (Desna)", "TSMC N40" }, + + /* Family 15h: Bulldozer Architecture (2011) */ + { 15, -1, -1, 21, 0, -1, -1, -1, { "FX(tm)-[468]###", 4 }, "FX (Zambezi)", "GF 32SHP" }, + { 15, -1, -1, 21, 1, -1, -1, -1, { "FX(tm)-[468]###", 4 }, "FX (Zambezi)", "GF 32SHP" }, + { 15, -1, -1, 21, 1, -1, -1, -1, { "Opteron(tm)", 2 }, "Opteron (Interlagos)", "GF 32SHP" }, + /* 2nd-gen, Piledriver core (2012): */ + { 15, -1, -1, 21, 2, -1, -1, -1, { "FX(tm)-[4689]###", 4 }, "FX (Vishera)", "GF 32SHP" }, + { 15, 0, -1, 21, 16, 4, -1, -1, { "Athlon(tm) X4 7##", 6 }, "Athlon X4 (Trinity)", "GF 32SHP" }, + { 15, 0, -1, 21, 16, 2, -1, -1, { "Athlon(tm) X2 3##", 6 }, "Athlon X2 (Trinity)", "GF 32SHP" }, + { 15, 0, -1, 21, 16, 2, -1, -1, { "Sempron(tm) X2 2##", 6 }, "Sempron X2 (Trinity)", "GF 32SHP" }, + { 15, 0, -1, 21, 16, -1, -1, -1, { "A[468]-5###", 4 }, "A-Series (Trinity)", "GF 32SHP" }, + { 15, 0, -1, 21, 16, -1, -1, -1, { "A10-5###", 4 }, "A-Series (Trinity)", "GF 32SHP" }, + { 15, 0, -1, 21, 16, -1, -1, -1, { "A[468]-4###M", 6 }, "A-Series (Trinity)", "GF 32SHP" }, + { 15, 0, -1, 21, 16, -1, -1, -1, { "A10-4###M", 6 }, "A-Series (Trinity)", "GF 32SHP" }, + { 15, 0, -1, 21, 19, -1, -1, -1, { "FX(tm)-6##K", 6 }, "FX (Richland)", "GF 32SHP" }, + { 15, 0, -1, 21, 19, 4, -1, -1, { "Athlon(tm) X4 7##", 6 }, "Athlon X4 (Richland)", "GF 32SHP" }, + { 15, 0, -1, 21, 19, 2, -1, -1, { "Athlon(tm) X2 3##", 6 }, "Athlon X2 (Richland)", "GF 32SHP" }, + { 15, 0, -1, 21, 19, 2, -1, -1, { "Sempron(tm) X2 2##", 6 }, "Sempron X2 (Richland)", "GF 32SHP" }, + { 15, 0, -1, 21, 19, -1, -1, -1, { "A4 PRO-7###B", 8 }, "A-Series (Richland)", "GF 32SHP" }, + { 15, 0, -1, 21, 19, -1, -1, -1, { "A[468]-[467]###", 4 }, "A-Series (Richland)", "GF 32SHP" }, + { 15, 0, -1, 21, 19, -1, -1, -1, { "A10-6###", 4 }, "A-Series (Richland)", "GF 32SHP" }, + { 15, 0, -1, 21, 19, -1, -1, -1, { "A[468]-5###M", 6 }, "A-Series (Richland)", "GF 32SHP" }, + { 15, 0, -1, 21, 19, -1, -1, -1, { "A10-5###M", 6 }, "A-Series (Richland)", "GF 32SHP" }, + { 15, 2, -1, 21, 2, -1, -1, -1, { "Opteron(tm)", 2 }, "Opteron (Abu Dhabi)", "GF 32SHP" }, + /* 3rd-gen, Steamroller core (2014): */ + { 15, 8, -1, 21, 48, -1, -1, -1, { "FX(tm)-7##K", 6 }, "FX (Kaveri)", "TSMC N28" }, + { 15, 8, -1, 21, 48, -1, -1, -1, { "FX(tm)-7###", 4 }, "FX (Kaveri)", "TSMC N28" }, + { 15, 8, -1, 21, 48, 4, -1, -1, { "Athlon(tm) X4 8##", 6 }, "Athlon X4 (Kaveri)", "TSMC N28" }, + { 15, 8, -1, 21, 48, 2, -1, -1, { "Athlon(tm) X2 4##", 6 }, "Athlon X2 (Kaveri)", "TSMC N28" }, + { 15, 8, -1, 21, 48, -1, -1, -1, { "A[468] PRO-[78]###B", 8 }, "A-Series (Kaveri)", "TSMC N28" }, + { 15, 8, -1, 21, 48, -1, -1, -1, { "A[468]-7###", 4 }, "A-Series (Kaveri)", "TSMC N28" }, + { 15, 8, -1, 21, 48, -1, -1, -1, { "A10 PRO-[78]###B", 8 }, "A-Series (Kaveri)", "TSMC N28" }, + { 15, 8, -1, 21, 48, -1, -1, -1, { "A10-7###", 4 }, "A-Series (Kaveri)", "TSMC N28" }, + { 15, 8, -1, 21, 56, -1, -1, -1, { "A[468]-[78]###", 4 }, "A-Series (Godavari)", "TSMC N28" }, + { 15, 8, -1, 21, 56, -1, -1, -1, { "A10-[78]###", 4 }, "A-Series (Godavari)", "TSMC N28" }, + { 15, 8, -1, 21, 56, 4, -1, -1, { "Athlon(tm) X4 8##", 6 }, "Athlon X4 (Godavari)", "TSMC N28" }, + { 15, 0, -1, 21, 48, -1, -1, -1, { "RX-###", 4 }, "R-Series (Bald Eagle)", "TSMC N28" }, + /* 4th-gen, Excavator core (2015): */ + { 15, 0, -1, 21, 96, -1, -1, -1, { "FX-8###P", 6 }, "FX (Carrizo)", "GF 28SHP" }, + { 15, 1, -1, 21, 96, 4, -1, -1, { "Athlon(tm) X4 8##", 6 }, "Athlon X4 (Carrizo)", "GF 28SHP" }, + { 15, 1, -1, 21, 96, -1, -1, -1, { "A[68] PRO-8###", 6 }, "A-Series (Carrizo)", "GF 28SHP" }, + { 15, 1, -1, 21, 96, -1, -1, -1, { "A[68]-[78]###", 4 }, "A-Series (Carrizo)", "GF 28SHP" }, + { 15, 1, -1, 21, 96, -1, -1, -1, { "A1[02] PRO-8###", 6 }, "A-Series (Carrizo)", "GF 28SHP" }, + { 15, 1, -1, 21, 96, -1, -1, -1, { "A1[02]-8###", 4 }, "A-Series (Carrizo)", "GF 28SHP" }, + { 15, 5, -1, 21, 101, -1, -1, -1, { "FX-9###P", 6 }, "FX (Bristol Ridge)", "GF 28SHP" }, + { 15, 5, -1, 21, 101, -1, -1, -1, { "Athlon(tm) X4 9##", 6 }, "Athlon X4 (Bristol Ridge)", "GF 28SHP" }, + { 15, 5, -1, 21, 101, -1, -1, -1, { "A[68] PRO-9###", 6 }, "A-Series (Bristol Ridge)", "GF 28SHP" }, + { 15, 5, -1, 21, 101, -1, -1, -1, { "A[68]-9###", 4 }, "A-Series (Bristol Ridge)", "GF 28SHP" }, + { 15, 5, -1, 21, 101, -1, -1, -1, { "A1[02] PRO-9###", 6 }, "A-Series (Bristol Ridge)", "GF 28SHP" }, + { 15, 5, -1, 21, 101, -1, -1, -1, { "A1[02]-9###", 4 }, "A-Series (Bristol Ridge)", "GF 28SHP" }, + { 15, 0, -1, 21, 112, 2, -1, -1, { "A[469]-9###", 4 }, "A-Series (Stoney Ridge)", "GF 28SHP" }, + { 15, 0, -1, 21, 112, -1, -1, -1, { "E2-9###", 4 }, "E-Series (Stoney Ridge)", "GF 28SHP" }, + { 15, 0, -1, 21, 96, -1, -1, -1, { "Opteron(tm) X3###", 6 }, "Opteron (Toronto)", "GF 28SHP" }, + + /* Family 16h: Jaguar Architecture (2013) */ + { 15, 0, -1, 22, 0, 4, -1, -1, { "Athlon(tm) X4 5##", 6 }, "Athlon X4 (Kabini)", "TSMC N28" }, + { 15, 0, -1, 22, 0, 4, -1, -1, { "Athlon(tm) 5###", 4 }, "Athlon X4 (Kabini)", "TSMC N28" }, + { 15, 0, -1, 22, 0, -1, -1, -1, { "Sempron(tm) [23]###", 4 }, "Sempron (Kabini)", "TSMC N28" }, + { 15, 0, -1, 22, 0, -1, -1, -1, { "E1-2###", 4 }, "E-Series (Kabini)", "TSMC N28" }, + { 15, 0, -1, 22, 0, -1, -1, -1, { "E2-3###", 4 }, "E-Series (Kabini)", "TSMC N28" }, + { 15, 0, -1, 22, 0, -1, -1, -1, { "A4 PRO-3###", 6 }, "A-Series (Kabini)", "TSMC N28" }, + { 15, 0, -1, 22, 0, -1, -1, -1, { "A[46]-5###", 4 }, "A-Series (Kabini)", "TSMC N28" }, + /* 2nd-gen, Puma core (2013): */ + { 15, 0, -1, 22, 48, 2, -1, -1, { "E1 Micro-62##T", 8 }, "E-Series (Mullins)", "GF 28SHP" }, + { 15, 0, -1, 22, 48, 4, -1, -1, { "A4 Micro-64##T", 8 }, "A-Series (Mullins)", "GF 28SHP" }, + { 15, 0, -1, 22, 48, 4, -1, -1, { "A10 Micro-67##T", 8 }, "A-Series (Mullins)", "GF 28SHP" }, + { 15, 0, 1, 22, 48, -1, -1, -1, { "E[12]-6###", 4 }, "E-Series (Beema)", "GF 28SHP" }, + { 15, 0, 1, 22, 48, -1, -1, -1, { "A[468]-6###", 4 }, "A-Series (Beema)", "GF 28SHP" }, + { 15, 0, 1, 22, 48, -1, -1, -1, { "GX-###", 4 }, "G-Series (Steppe Eagle)", "GF 28SHP" }, + + /* Family 17h */ + /* Zen (2017) => https://en.wikichip.org/wiki/amd/microarchitectures/zen */ + { 15, -1, -1, 23, 1, -1, -1, -1, { "EPYC 7##1", 4 }, "EPYC (Naples)", "GF 14LP" }, + { 15, -1, -1, 23, 1, -1, -1, -1, { "Threadripper 1###", 4 }, "Threadripper (Whitehaven)", "GF 14LP" }, + { 15, -1, -1, 23, 1, -1, -1, -1, { "Ryzen 7 PRO 1###", 8 }, "Ryzen 7 PRO (Summit Ridge)", "GF 14LP" }, + { 15, -1, -1, 23, 1, -1, -1, -1, { "Ryzen 7 1###", 6 }, "Ryzen 7 (Summit Ridge)", "GF 14LP" }, + { 15, -1, -1, 23, 1, -1, -1, -1, { "Ryzen 5 PRO 1###", 8 }, "Ryzen 5 PRO (Summit Ridge)", "GF 14LP" }, + { 15, -1, -1, 23, 1, -1, -1, -1, { "Ryzen 5 1###", 6 }, "Ryzen 5 (Summit Ridge)", "GF 14LP" }, + { 15, -1, -1, 23, 1, -1, -1, -1, { "Ryzen 3 PRO 1###", 8 }, "Ryzen 3 PRO (Summit Ridge)", "GF 14LP" }, + { 15, -1, -1, 23, 1, -1, -1, -1, { "Ryzen 3 1###", 6 }, "Ryzen 3 (Summit Ridge)", "GF 14LP" }, + { 15, -1, -1, 23, 17, -1, -1, -1, { "Ryzen PRO 7 2###", 8 }, "Ryzen 7 PRO (Raven Ridge)", "GF 14LP" }, + { 15, -1, -1, 23, 17, -1, -1, -1, { "Ryzen 7 2###", 6 }, "Ryzen 7 (Raven Ridge)", "GF 14LP" }, + { 15, -1, -1, 23, 17, -1, -1, -1, { "Ryzen PRO 5 2###", 8 }, "Ryzen 5 PRO (Raven Ridge)", "GF 14LP" }, + { 15, -1, -1, 23, 17, -1, -1, -1, { "Ryzen 5 2###", 6 }, "Ryzen 5 (Raven Ridge)", "GF 14LP" }, + { 15, -1, -1, 23, 17, -1, -1, -1, { "Ryzen PRO 3 2###", 8 }, "Ryzen 3 PRO (Raven Ridge)", "GF 14LP" }, + { 15, -1, -1, 23, 17, -1, -1, -1, { "Ryzen 3 2###", 6 }, "Ryzen 3 (Raven Ridge)", "GF 14LP" }, + { 15, -1, -1, 23, 17, -1, -1, -1, { "Athlon", 2 }, "Athlon (Raven Ridge)", "GF 14LP" }, + { 15, -1, -1, 23, 32, -1, -1, -1, { "Ryzen 3 3###", 6 }, "Ryzen 3 (Dali)", "GF 14LP" }, + { 15, -1, -1, 23, 32, -1, -1, -1, { "Athlon", 2 }, "Athlon (Dali)", "GF 14LP" }, + { 15, -1, 1, 23, 32, -1, -1, -1, { "", 0 }, "Dali", "GF 14LP" }, /* AMD 3020e */ + /* Zen+ (2018) => https://en.wikichip.org/wiki/amd/microarchitectures/zen%2B */ + { 15, -1, -1, 23, 8, -1, -1, -1, { "Threadripper 2###", 4 }, "Threadripper (Colfax)", "GF 12LP" }, + { 15, -1, -1, 23, 8, -1, -1, -1, { "Ryzen 7 PRO 2###", 8 }, "Ryzen 7 PRO (Pinnacle Ridge)", "GF 12LP" }, + { 15, -1, -1, 23, 8, -1, -1, -1, { "Ryzen 7 2###", 6 }, "Ryzen 7 (Pinnacle Ridge)", "GF 12LP" }, + { 15, -1, -1, 23, 8, -1, -1, -1, { "Ryzen 5 PRO 2###", 8 }, "Ryzen 5 PRO (Pinnacle Ridge)", "GF 12LP" }, + { 15, -1, -1, 23, 8, -1, -1, -1, { "Ryzen 5 2###", 6 }, "Ryzen 5 (Pinnacle Ridge)", "GF 12LP" }, + { 15, -1, -1, 23, 8, -1, -1, -1, { "Ryzen 3 PRO 2###", 8 }, "Ryzen 3 PRO (Pinnacle Ridge)", "GF 12LP" }, + { 15, -1, -1, 23, 8, -1, -1, -1, { "Ryzen 3 2###", 6 }, "Ryzen 3 (Pinnacle Ridge)", "GF 12LP" }, + { 15, -1, -1, 23, 24, -1, -1, -1, { "Ryzen 7 PRO 3###", 8 }, "Ryzen 7 PRO (Picasso)", "GF 12LP" }, + { 15, -1, -1, 23, 24, -1, -1, -1, { "Ryzen 7 3###", 6 }, "Ryzen 7 (Picasso)", "GF 12LP" }, + { 15, -1, -1, 23, 24, -1, -1, -1, { "Ryzen 5 PRO 3###", 8 }, "Ryzen 5 PRO (Picasso)", "GF 12LP" }, + { 15, -1, -1, 23, 24, -1, -1, -1, { "Ryzen 5 3###", 6 }, "Ryzen 5 (Picasso)", "GF 12LP" }, + { 15, -1, -1, 23, 24, -1, -1, -1, { "Ryzen 3 PRO 3###", 8 }, "Ryzen 3 PRO (Picasso)", "GF 12LP" }, + { 15, -1, -1, 23, 24, -1, -1, -1, { "Ryzen 3 3###", 6 }, "Ryzen 3 (Picasso)", "GF 12LP" }, + { 15, -1, -1, 23, 24, -1, -1, -1, { "Athlon", 2 }, "Athlon (Picasso)", "GF 12LP" }, + /* Zen 2 (2019) => https://en.wikichip.org/wiki/amd/microarchitectures/zen_2 */ + { 15, -1, -1, 23, 49, -1, -1, -1, { "EPYC 7##2", 4 }, "EPYC (Rome)", "TSMC N7FF" }, + { 15, -1, -1, 23, 49, -1, -1, -1, { "Threadripper PRO 3###WX", 10 }, "Threadripper PRO (Castle Peak)", "TSMC N7FF" }, + { 15, -1, -1, 23, 49, -1, -1, -1, { "Threadripper 3###X", 6 }, "Threadripper (Castle Peak)", "TSMC N7FF" }, + { 15, -1, -1, 23, 113, -1, -1, -1, { "Ryzen 9 PRO 3###", 8 }, "Ryzen 9 PRO (Matisse)", "TSMC N7FF" }, + { 15, -1, -1, 23, 113, -1, -1, -1, { "Ryzen 9 3###", 6 }, "Ryzen 9 (Matisse)", "TSMC N7FF" }, + { 15, -1, -1, 23, 113, -1, -1, -1, { "Ryzen 7 PRO 3###", 8 }, "Ryzen 7 PRO (Matisse)", "TSMC N7FF" }, + { 15, -1, -1, 23, 113, -1, -1, -1, { "Ryzen 7 3###", 6 }, "Ryzen 7 (Matisse)", "TSMC N7FF" }, + { 15, -1, -1, 23, 113, -1, -1, -1, { "Ryzen 5 PRO 3###", 8 }, "Ryzen 5 PRO (Matisse)", "TSMC N7FF" }, + { 15, -1, -1, 23, 113, -1, -1, -1, { "Ryzen 5 3###", 6 }, "Ryzen 5 (Matisse)", "TSMC N7FF" }, + { 15, -1, -1, 23, 113, -1, -1, -1, { "Ryzen 3 PRO 3###", 8 }, "Ryzen 3 PRO (Matisse)", "TSMC N7FF" }, + { 15, -1, -1, 23, 113, -1, -1, -1, { "Ryzen 3 3###", 6 }, "Ryzen 3 (Matisse)", "TSMC N7FF" }, + { 15, -1, -1, 23, 96, -1, -1, -1, { "Ryzen 9 PRO 4###", 8 }, "Ryzen 9 PRO (Renoir)", "TSMC N7FF" }, + { 15, -1, -1, 23, 96, -1, -1, -1, { "Ryzen 9 4###", 6 }, "Ryzen 9 (Renoir)", "TSMC N7FF" }, + { 15, -1, -1, 23, 96, -1, -1, -1, { "Ryzen 7 PRO 4###", 8 }, "Ryzen 7 PRO (Renoir)", "TSMC N7FF" }, + { 15, -1, -1, 23, 96, -1, -1, -1, { "Ryzen 7 4###", 6 }, "Ryzen 7 (Renoir)", "TSMC N7FF" }, + { 15, -1, -1, 23, 96, -1, -1, -1, { "Ryzen 5 PRO 4###", 8 }, "Ryzen 5 PRO (Renoir)", "TSMC N7FF" }, + { 15, -1, -1, 23, 96, -1, -1, -1, { "Ryzen 5 4###", 6 }, "Ryzen 5 (Renoir)", "TSMC N7FF" }, + { 15, -1, -1, 23, 96, -1, -1, -1, { "Ryzen 3 PRO 4###", 8 }, "Ryzen 3 PRO (Renoir)", "TSMC N7FF" }, + { 15, -1, -1, 23, 96, -1, -1, -1, { "Ryzen 3 4###", 6 }, "Ryzen 3 (Renoir)", "TSMC N7FF" }, + { 15, -1, -1, 23, 104, -1, -1, -1, { "Ryzen 7 5###", 6 }, "Ryzen 7 (Lucienne)", "TSMC N7FF" }, + { 15, -1, -1, 23, 104, -1, -1, -1, { "Ryzen 5 5###", 6 }, "Ryzen 5 (Lucienne)", "TSMC N7FF" }, + { 15, -1, -1, 23, 104, -1, -1, -1, { "Ryzen 3 5###", 6 }, "Ryzen 3 (Lucienne)", "TSMC N7FF" }, + { 15, -1, -1, 23, 71, -1, -1, -1, { "Desktop Kit", 4 }, "Desktop Kit (Zen 2)", "TSMC N7FF" }, /* 4700S Desktop Kit */ + { 15, -1, -1, 23, 132, -1, -1, -1, { "Desktop Kit", 4 }, "Desktop Kit (Zen 2)", "TSMC N7FF" }, /* 4800S Desktop Kit */ + { 15, -1, 2, 23, 144, -1, -1, -1, { "Custom APU", 4 }, "Van Gogh", "TSMC N7FF" }, /* Custom APU 0405 */ + { 15, -1, 0, 23, 145, -1, -1, -1, { "Custom APU", 4 }, "Van Gogh", "TSMC N7FF" }, /* Custom APU 0932 */ + { 15, -1, -1, 23, 160, -1, -1, -1, { "Ryzen 5 7###", 6 }, "Ryzen 5 (Mendocino)", "TSMC N6" }, + { 15, -1, -1, 23, 160, -1, -1, -1, { "Ryzen 3 7###", 6 }, "Ryzen 3 (Mendocino)", "TSMC N6" }, + { 15, -1, -1, 23, 160, -1, -1, -1, { "Athlon", 2 }, "Athlon (Mendocino)", "TSMC N6" }, + + /* Family 18h */ + /* Zen Architecture for Hygon (2018) => https://en.wikichip.org/wiki/hygon/microarchitectures/dhyana */ + { 15, -1, -1, 24, 0, -1, -1, -1, { "C86", 2 }, "C86 (Dhyana)", UNKN_STR }, + + /* Family 19h */ + /* Zen 3 (2020) => https://en.wikichip.org/wiki/amd/microarchitectures/zen_3 */ + { 15, -1, -1, 25, 1, -1, -1, -1, { "EPYC 7##3", 4 }, "EPYC (Milan)", "TSMC N7FF" }, + { 15, -1, -1, 25, 8, -1, -1, -1, { "Threadripper PRO 5###WX", 10 }, "Threadripper PRO (Chagall)", "TSMC N7FF" }, + { 15, -1, -1, 25, 33, -1, -1, -1, { "Ryzen 9 PRO 5###", 8 }, "Ryzen 9 PRO (Vermeer)", "TSMC N7FF" }, + { 15, -1, -1, 25, 33, -1, -1, -1, { "Ryzen 9 5###", 6 }, "Ryzen 9 (Vermeer)", "TSMC N7FF" }, + { 15, -1, -1, 25, 33, -1, -1, -1, { "Ryzen 7 PRO 5###", 8 }, "Ryzen 7 PRO (Vermeer)", "TSMC N7FF" }, + { 15, -1, -1, 25, 33, -1, -1, -1, { "Ryzen 7 5###", 6 }, "Ryzen 7 (Vermeer)", "TSMC N7FF" }, + { 15, -1, -1, 25, 33, -1, -1, -1, { "Ryzen 5 PRO 5###", 8 }, "Ryzen 5 PRO (Vermeer)", "TSMC N7FF" }, + { 15, -1, -1, 25, 33, -1, -1, -1, { "Ryzen 5 5###", 6 }, "Ryzen 5 (Vermeer)", "TSMC N7FF" }, + { 15, -1, -1, 25, 33, -1, -1, -1, { "Ryzen 3 PRO 5###", 8 }, "Ryzen 3 PRO (Vermeer)", "TSMC N7FF" }, + { 15, -1, -1, 25, 33, -1, -1, -1, { "Ryzen 3 5###", 6 }, "Ryzen 3 (Vermeer)", "TSMC N7FF" }, + { 15, -1, -1, 25, 80, -1, -1, -1, { "Ryzen 9 PRO 5##0[HU]", 10 }, "Ryzen 9 PRO (Cezanne)", "TSMC N7FF" }, + { 15, -1, -1, 25, 80, -1, -1, -1, { "Ryzen 9 5##0[HU]", 8 }, "Ryzen 9 (Cezanne)", "TSMC N7FF" }, + { 15, -1, -1, 25, 80, -1, -1, -1, { "Ryzen 7 PRO 5##0[HU]", 10 }, "Ryzen 7 PRO (Cezanne)", "TSMC N7FF" }, + { 15, -1, -1, 25, 80, -1, -1, -1, { "Ryzen 7 5##0[HU]", 8 }, "Ryzen 7 (Cezanne)", "TSMC N7FF" }, + { 15, -1, -1, 25, 80, -1, -1, -1, { "Ryzen 5 PRO 5##0[HU]", 10 }, "Ryzen 5 PRO (Cezanne)", "TSMC N7FF" }, + { 15, -1, -1, 25, 80, -1, -1, -1, { "Ryzen 5 5##0[HU]", 8 }, "Ryzen 5 (Cezanne)", "TSMC N7FF" }, + { 15, -1, -1, 25, 80, -1, -1, -1, { "Ryzen 3 PRO 5##0[HU]", 10 }, "Ryzen 3 PRO (Cezanne)", "TSMC N7FF" }, + { 15, -1, -1, 25, 80, -1, -1, -1, { "Ryzen 3 5##0[HU]", 8 }, "Ryzen 3 (Cezanne)", "TSMC N7FF" }, + { 15, -1, -1, 25, 80, -1, -1, -1, { "Ryzen 7 5##5U", 8 }, "Ryzen 7 (Barceló)", "TSMC N7FF" }, /* Ryzen 7 5825U */ + { 15, -1, -1, 25, 80, -1, -1, -1, { "Ryzen 5 5##5U", 8 }, "Ryzen 5 (Barceló)", "TSMC N7FF" }, /* Ryzen 5 5625U */ + { 15, -1, -1, 25, 80, -1, -1, -1, { "Ryzen 3 PRO 5##5U", 10 }, "Ryzen 3 PRO (Barceló)", "TSMC N7FF" }, /* Ryzen 3 PRO 5475U */ + { 15, -1, -1, 25, 80, -1, -1, -1, { "Ryzen 3 5##5C", 8 }, "Ryzen 3 (Barceló)", "TSMC N7FF" }, /* Ryzen 3 5125C */ + /* Zen 3+ (2022) */ + { 15, -1, -1, 25, 68, -1, -1, -1, { "Ryzen 9 PRO 6###", 8 }, "Ryzen 9 PRO (Rembrandt)", "TSMC N6" }, + { 15, -1, -1, 25, 68, -1, -1, -1, { "Ryzen 9 6###", 6 }, "Ryzen 9 (Rembrandt)", "TSMC N6" }, + { 15, -1, -1, 25, 68, -1, -1, -1, { "Ryzen 7 PRO 6###", 8 }, "Ryzen 7 PRO (Rembrandt)", "TSMC N6" }, + { 15, -1, -1, 25, 68, -1, -1, -1, { "Ryzen 7 6###", 6 }, "Ryzen 7 (Rembrandt)", "TSMC N6" }, + { 15, -1, -1, 25, 68, -1, -1, -1, { "Ryzen 5 PRO 6###", 8 }, "Ryzen 5 PRO (Rembrandt)", "TSMC N6" }, + { 15, -1, -1, 25, 68, -1, -1, -1, { "Ryzen 5 6###", 6 }, "Ryzen 5 (Rembrandt)", "TSMC N6" }, + { 15, -1, -1, 25, 68, -1, -1, -1, { "Ryzen 3 PRO 6###", 8 }, "Ryzen 3 PRO (Rembrandt)", "TSMC N6" }, + { 15, -1, -1, 25, 68, -1, -1, -1, { "Ryzen 3 6###", 6 }, "Ryzen 3 (Rembrandt)", "TSMC N6" }, + { 15, -1, -1, 25, 68, -1, -1, -1, { "Ryzen 7 7###", 6 }, "Ryzen 7 (Rembrandt-R)", "TSMC N6" }, + { 15, -1, -1, 25, 68, -1, -1, -1, { "Ryzen 5 7###", 6 }, "Ryzen 5 (Rembrandt-R)", "TSMC N6" }, + { 15, -1, -1, 25, 68, -1, -1, -1, { "Ryzen 3 7###", 6 }, "Ryzen 3 (Rembrandt-R)", "TSMC N6" }, + /* Zen 4 (2022) => https://en.wikichip.org/wiki/amd/microarchitectures/zen_4 */ + { 15, -1, -1, 25, 17, -1, -1, -1, { "EPYC 9##4", 4 }, "EPYC (Genoa)", "TSMC N5" }, + { 15, -1, -1, 25, 24, -1, -1, -1, { "Threadripper PRO 7###WX", 10 }, "Threadripper PRO (Storm Peak)", "TSMC N5" }, + { 15, -1, -1, 25, 24, -1, -1, -1, { "Threadripper 7###X", 6 }, "Threadripper (Storm Peak)", "TSMC N5" }, + /* => Raphael (7000 series, Zen 4/RDNA2 based) */ + { 15, -1, 2, 25, 97, -1, -1, -1, { "Ryzen 9 7###", 6 }, "Ryzen 9 (Raphael)", "TSMC N5" }, + { 15, -1, 2, 25, 97, -1, -1, -1, { "Ryzen 7 7###", 6 }, "Ryzen 7 (Raphael)", "TSMC N5" }, + { 15, -1, 2, 25, 97, -1, -1, -1, { "Ryzen 5 7###", 6 }, "Ryzen 5 (Raphael)", "TSMC N5" }, + { 15, -1, 2, 25, 97, -1, -1, -1, { "Ryzen 3 7###", 6 }, "Ryzen 3 (Raphael)", "TSMC N5" }, + /* => Dragon Range (7045 series, Zen 4/RDNA2 based) */ + { 15, -1, -1, 25, 97, -1, -1, -1, { "Ryzen 9 7###H", 8 }, "Ryzen 9 (Dragon Range)", "TSMC N5" }, + { 15, -1, -1, 25, 97, -1, -1, -1, { "Ryzen 7 7###H", 8 }, "Ryzen 7 (Dragon Range)", "TSMC N5" }, + { 15, -1, -1, 25, 97, -1, -1, -1, { "Ryzen 5 7###H", 8 }, "Ryzen 5 (Dragon Range)", "TSMC N5" }, + /* => Phoenix (7040 series, Zen 4/RDNA3/XDNA based) */ + { 15, -1, -1, 25, 116, -1, -1, -1, { "Ryzen 9 PRO 7###[HU]", 10 }, "Ryzen 9 PRO (Phoenix)", "TSMC N4" }, + { 15, -1, -1, 25, 116, -1, -1, -1, { "Ryzen 9 7###[HU]", 8 }, "Ryzen 9 (Phoenix)", "TSMC N4" }, + { 15, -1, -1, 25, 116, -1, -1, -1, { "Ryzen 7 PRO 7###[HU]", 10 }, "Ryzen 7 PRO (Phoenix)", "TSMC N4" }, + { 15, -1, -1, 25, 116, -1, -1, -1, { "Ryzen 7 7###[HU]", 8 }, "Ryzen 7 (Phoenix)", "TSMC N4" }, + { 15, -1, -1, 25, 116, -1, -1, -1, { "Ryzen 5 PRO 7###[HU]", 10 }, "Ryzen 5 PRO (Phoenix)", "TSMC N4" }, + { 15, -1, -1, 25, 116, -1, -1, -1, { "Ryzen 5 7###[HU]", 8 }, "Ryzen 5 (Phoenix)", "TSMC N4" }, + { 15, -1, -1, 25, 116, -1, -1, -1, { "Ryzen 3 PRO 7###[HU]", 10 }, "Ryzen 3 PRO (Phoenix)", "TSMC N4" }, + { 15, -1, -1, 25, 116, -1, -1, -1, { "Ryzen 3 7###[HU]", 8 }, "Ryzen 3 (Phoenix)", "TSMC N4" }, + { 15, -1, -1, 25, 116, -1, -1, -1, { "Ryzen Z1", 4 }, "Ryzen Z1 (Phoenix)", "TSMC N4" }, + /* => Phoenix (8000 series, Zen 4 based) */ + { 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 7 8###F", 8 }, "Ryzen 7 (Phoenix)", "TSMC N4" }, + { 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 5 8###F", 8 }, "Ryzen 5 (Phoenix)", "TSMC N4" }, + /* => Phoenix (8000 series with Radeon Graphics, Zen 4/RDNA3/XDNA based) */ + { 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 9 PRO 8###G", 10 }, "Ryzen 9 PRO (Phoenix)", "TSMC N4" }, + { 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 9 8###G", 8 }, "Ryzen 9 (Phoenix)", "TSMC N4" }, + { 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 7 PRO 8###G", 10 }, "Ryzen 7 PRO (Phoenix)", "TSMC N4" }, + { 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 7 8###G", 8 }, "Ryzen 7 (Phoenix)", "TSMC N4" }, + { 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 5 PRO 8###G", 10 }, "Ryzen 5 PRO (Phoenix)", "TSMC N4" }, + { 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 5 8###G", 8 }, "Ryzen 5 (Phoenix)", "TSMC N4" }, + { 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 3 PRO 8###G", 10 }, "Ryzen 3 PRO (Phoenix)", "TSMC N4" }, + { 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 3 8###G", 8 }, "Ryzen 3 (Phoenix)", "TSMC N4" }, + /* => Hawk Point (8040 series, Zen 4/RDNA3/XDNA based) */ + { 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 9 PRO 8###[HU]", 10 }, "Ryzen 9 PRO (Hawk Point)", "TSMC N4" }, + { 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 9 8###[HU]", 8 }, "Ryzen 9 (Hawk Point)", "TSMC N4" }, + { 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 7 PRO 8###[HU]", 10 }, "Ryzen 7 PRO (Hawk Point)", "TSMC N4" }, + { 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 7 8###[HU]", 8 }, "Ryzen 7 (Hawk Point)", "TSMC N4" }, + { 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 5 PRO 8###[HU]", 10 }, "Ryzen 5 PRO (Hawk Point)", "TSMC N4" }, + { 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 5 8###[HU]", 8 }, "Ryzen 5 (Hawk Point)", "TSMC N4" }, + { 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 3 PRO 8###[HU]", 10 }, "Ryzen 3 PRO (Hawk Point)", "TSMC N4" }, + { 15, -1, -1, 25, 117, -1, -1, -1, { "Ryzen 3 8###[HU]", 8 }, "Ryzen 3 (Hawk Point)", "TSMC N4" }, + /* Zen 5 (2024) => https://en.wikichip.org/wiki/amd/microarchitectures/zen_5 */ + { 15, -1, -1, 26, 2, -1, -1, -1, { "EPYC 9##5", 4 }, "EPYC (Turin)", "TSMC N4X" }, + { 15, -1, -1, 26, 17, -1, -1, -1, { "EPYC 9##5", 4 }, "EPYC (Turin Dense)", "TSMC N3E" }, + { 15, -1, -1, 26, 8, -1, -1, -1, { "Threadripper PRO 9###WX", 10 }, "Threadripper PRO (Shimada Peak)", "TSMC N4" }, + { 15, -1, -1, 26, 8, -1, -1, -1, { "Threadripper 9###X", 6 }, "Threadripper (Shimada Peak)", "TSMC N4" }, + /* => Granite Ridge (9000 series, Zen 5 based) */ + { 15, -1, -1, 26, 68, -1, -1, -1, { "Ryzen 9 PRO 9###", 8 }, "Ryzen 9 PRO (Granite Ridge)", "TSMC N4" }, + { 15, -1, -1, 26, 68, -1, -1, -1, { "Ryzen 9 9###", 6 }, "Ryzen 9 (Granite Ridge)", "TSMC N4" }, + { 15, -1, -1, 26, 68, -1, -1, -1, { "Ryzen 7 PRO 9###", 8 }, "Ryzen 7 PRO (Granite Ridge)", "TSMC N4" }, + { 15, -1, -1, 26, 68, -1, -1, -1, { "Ryzen 7 9###", 6 }, "Ryzen 7 (Granite Ridge)", "TSMC N4" }, + { 15, -1, -1, 26, 68, -1, -1, -1, { "Ryzen 5 PRO 9###", 8 }, "Ryzen 5 PRO (Granite Ridge)", "TSMC N4" }, + { 15, -1, -1, 26, 68, -1, -1, -1, { "Ryzen 5 9###", 6 }, "Ryzen 5 (Granite Ridge)", "TSMC N4" }, + { 15, -1, -1, 26, 68, -1, -1, -1, { "Ryzen 3 PRO 9###", 8 }, "Ryzen 3 PRO (Granite Ridge)", "TSMC N4" }, + { 15, -1, -1, 26, 68, -1, -1, -1, { "Ryzen 3 9###", 6 }, "Ryzen 3 (Granite Ridge)", "TSMC N4" }, + /* => Strix Point and Krackan Point (Zen 5/RDNA3.5/XDNA2 based) */ + { 15, -1, -1, 26, 36, -1, -1, -1, { "Ryzen AI 9 HX PRO", 10 }, "Ryzen AI 9 PRO (Strix Point)", "TSMC N4P" }, + { 15, -1, -1, 26, 36, -1, -1, -1, { "Ryzen AI 9", 6 }, "Ryzen AI 9 (Strix Point)", "TSMC N4P" }, + { 15, -1, -1, 26, 36, -1, -1, -1, { "Ryzen AI 7 PRO", 8 }, "Ryzen AI 7 PRO (Strix Point)", "TSMC N4P" }, /* Ryzen AI 7 PRO 360 */ + { 15, -1, -1, 26, 96, -1, -1, -1, { "Ryzen AI 7 PRO", 8 }, "Ryzen AI 7 PRO (Krackan Point)", "TSMC N4P" }, /* Ryzen AI 7 PRO 350 */ + { 15, -1, -1, 26, 96, -1, -1, -1, { "Ryzen AI 7", 6 }, "Ryzen AI 7 (Krackan Point)", "TSMC N4P" }, /* Ryzen AI 7 350 */ + { 15, -1, -1, 26, 96, -1, -1, -1, { "Ryzen AI 5 PRO", 8 }, "Ryzen AI 5 PRO (Krackan Point)", "TSMC N4P" }, /* Ryzen AI 5 PRO 340 */ + { 15, -1, -1, 26, 96, -1, -1, -1, { "Ryzen AI 5", 6 }, "Ryzen AI 5 (Krackan Point)", "TSMC N4P" }, /* Ryzen AI 5 340 */ + /* => Strix Halo (Zen 5/RDNA3.5/XDNA2 based) */ + { 15, -1, -1, 26, 112, -1, -1, -1, { "Ryzen AI MAX+ PRO", 10 }, "Ryzen AI MAX+ PRO (Strix Halo)", "TSMC N4P" }, /* Ryzen AI MAX+ PRO 395 */ + { 15, -1, -1, 26, 112, -1, -1, -1, { "Ryzen AI MAX+", 8 }, "Ryzen AI MAX+ (Strix Halo)", "TSMC N4P" }, /* Ryzen AI MAX+ 395 */ + { 15, -1, -1, 26, 112, -1, -1, -1, { "Ryzen AI MAX PRO", 8 }, "Ryzen AI MAX PRO (Strix Halo)", "TSMC N4P" }, + { 15, -1, -1, 26, 112, -1, -1, -1, { "Ryzen AI MAX", 6 }, "Ryzen AI MAX (Strix Halo)", "TSMC N4P" }, +// F M S EF EM #cores L2$ L3$ Pattern Codename Technology +}; + +/********************************************************************************** */ + +// https://github.com/anrieff/libcpuid/blob/2e4456ae0165db3155da2e8fba92afd5c090ca1b/libcpuid/recog_centaur.c +/* + * Copyright 2023 Veselin Georgiev, + * anrieffNOSPAM @ mgail_DOT.com (convert to gmail) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +const struct match_entry_t cpudb_centaur[] = { +// F M S EF EM #cores L2$ L3$ Pattern Codename Technology + { -1, -1, -1, -1, -1, -1, -1, -1, { "", 0 }, "Unknown Centaur CPU", "" }, +// F M S EF EM #cores L2$ L3$ Pattern Codename Technology + + + /* VIA */ +// F M S EF EM #cores L2$ L3$ Pattern Codename Technology + { 6, -1, -1, -1, -1, -1, -1, -1, { "VIA", 2 }, "Unknown VIA CPU", "" }, + + /* Samuel (2000, 180 nm) */ + { 6, 6, -1, -1, -1, -1, -1, -1, { "VIA Samuel", 4 }, "VIA Cyrix III (Samuel)", "180 nm" }, + /* Samuel 2 (2001, 150 nm) */ + { 6, 7, -1, -1, -1, -1, -1, -1, { "VIA Samuel 2", 6 }, "VIA C3 (Samuel 2)", "150 nm" }, + /* Ezra (2001, 130 nm) */ + { 6, 7, -1, -1, -1, -1, -1, -1, { "VIA Ezra", 4 }, "VIA C3 (Ezra)", "130 nm" }, + { 6, 8, -1, -1, -1, -1, -1, -1, { "VIA C3 Ezra", 6 }, "VIA C3 (Ezra-T)", "130 nm" }, + /* Nehemiah (2003, 130 nm) */ + { 6, 9, -1, -1, -1, -1, -1, -1, { "VIA Nehemiah", 4 }, "VIA C3 (Nehemiah)", "130 nm" }, + /* Esther (2005, 90 nm) */ + { 6, 10, -1, -1, -1, -1, -1, -1, { "VIA Esther", 4 }, "VIA C7 (Esther)", "90 nm" }, + { 6, 13, -1, -1, -1, -1, -1, -1, { "VIA C7-M", 4 }, "VIA C7-M (Esther)", "90 nm" }, + /* Isaiah (2008, 65 nm) */ + { 6, 15, -1, -1, -1, -1, -1, -1, { "VIA Nano", 4 }, "VIA Nano (Isaiah)", "65 nm" }, + { 6, 15, -1, -1, -1, 1, -1, -1, { "VIA Nano", 4 }, "VIA Nano (Isaiah)", "65 nm" }, + { 6, 15, -1, -1, -1, 2, -1, -1, { "VIA Nano", 4 }, "VIA Nano X2 (Isaiah)", "65 nm" }, + { 6, 15, -1, -1, -1, -1, -1, -1, { "VIA QuadCore", 4 }, "VIA Nano X4 (Isaiah)", "65 nm" }, + { 6, 15, -1, -1, -1, 4, -1, -1, { "VIA Eden X4", 6 }, "VIA Eden X4 (Isaiah)", "65 nm" }, +// F M S EF EM #cores L2$ L3$ Pattern Codename Technology + + + /* Zhaoxin */ +// F M S EF EM #cores L2$ L3$ Pattern Codename Technology + { 7, -1, -1, -1, -1, -1, -1, -1, {"ZHAOXIN", 2 }, "Unknown Zhaoxin CPU", "" }, + + /* Zhangjiang (2015, 28 nm) */ + { 7, -1, -1, -1, 15, -1, -1, -1, { "ZHAOXIN KaisHeng KH-C", 8 }, "Zhaoxin KaisHeng (ZhangJiang)", "28 nm" }, // C+ (4000) + { 7, -1, -1, -1, 15, -1, -1, -1, { "ZHAOXIN KaiXian ZX-C", 8 }, "Zhaoxin KaiXian (ZhangJiang)", "28 nm" }, // C/C+ (4000) + /* WuDaoKou (2017, 28 nm) */ + { 7, -1, -1, -1, 27, -1, -1, -1, { "ZHAOXIN KaisHeng KH-20###", 8 }, "Zhaoxin KaisHeng (WuDaoKou)", "28 nm" }, // KH (20000) + { 7, -1, -1, -1, 27, -1, -1, -1, { "ZHAOXIN KaiXian KX-5###", 8 }, "Zhaoxin KaiXian (WuDaoKou)", "28 nm" }, // KX (5000) + { 7, -1, -1, -1, 27, -1, -1, -1, { "ZHAOXIN KaiXian KX-U5###", 8 }, "Zhaoxin KaiXian (WuDaoKou)", "28 nm" }, // KX (U5000) + /* LuJiaZui (2019, 16 nm) */ + { 7, -1, -1, -1, 59, -1, -1, -1, { "ZHAOXIN KaisHeng KH-30###", 8 }, "Zhaoxin KaisHeng (LuJiaZui)", "16 nm" }, // KH (30000) + { 7, -1, -1, -1, 59, -1, -1, -1, { "ZHAOXIN KaiXian KX-6###", 8 }, "Zhaoxin KaiXian (LuJiaZui)", "16 nm" }, // KX (6000) + { 7, -1, -1, -1, 59, -1, -1, -1, { "ZHAOXIN KaiXian KX-U6###", 8 }, "Zhaoxin KaiXian (LuJiaZui)", "16 nm" }, // KX (U6000) + /* Yongfeng (2022, 16 nm) */ + { 7, -1, -1, -1, 91, -1, -1, -1, { "ZHAOXIN KaisHeng KH-40###", 8 }, "Zhaoxin KaisHeng (Yongfeng)", "16 nm" }, // KH (40000) + { 7, -1, -1, -1, 91, -1, -1, -1, { "ZHAOXIN KaiXian KX-7###", 8 }, "Zhaoxin KaiXian (Yongfeng)", "16 nm" }, // KX (7000) +// F M S EF EM #cores L2$ L3$ Pattern Codename Technology +}; + +// clang-format on + +/////////////////////////////////////////////////////////////////////////////////////////////// + +static bool match_pattern_core(const char* p, const char* b) { + while (*p && *b) { + if (*p == '#') { + // '#' digit + if (!ffCharIsDigit(*b)) return false; + p++; b++; + } else if (*p == '[') { + // '[' chars + p++; + bool found = false; + while (*p && *p != ']') { + if (*p == *b) found = true; + p++; + } + if (!found) return false; + if (*p == ']') p++; + b++; + } else { + // char + if (*p != *b) return false; + p++; b++; + } + } + + // ignore suffix + return (*p == '\0'); +} + +static bool match_brand_pattern(const char* pattern, const char* brand) { + if (pattern[0] == '\0') return true; + if (brand[0] == '\0') return false; + + for (const char* b = brand; *b != '\0'; b++) { + if (match_pattern_core(pattern, b)) { + return true; + } + } + return false; +} + +bool ffCPUDetectX86Specific(FFCPUResult* cpu) { + // Ref: https://github.com/anrieff/libcpuid/blob/2e4456ae0165db3155da2e8fba92afd5c090ca1b/libcpuid/cpuid_main.c#L1096 + unsigned int eax, ebx, ecx, edx; + + // Vendor (CPUID Leaf 0) + if (!__get_cpuid(0, &eax, &ebx, &ecx, &edx)) { + return false; + } + + ffStrbufClear(&cpu->vendor); + ffStrbufEnsureFixedLengthFree(&cpu->vendor, 12); + memcpy(cpu->vendor.chars + 0, &ebx, 4); + memcpy(cpu->vendor.chars + 4, &edx, 4); + memcpy(cpu->vendor.chars + 8, &ecx, 4); + cpu->vendor.chars[12] = '\0'; + cpu->vendor.length = 12; + + // Brand String (CPUID Leaves 0x80000002 - 0x80000004) + char brand[49] = {}; + unsigned int ext_eax; + if (__get_cpuid(0x80000000, &ext_eax, &ebx, &ecx, &edx)) { + if (ext_eax >= 0x80000004) { + unsigned int* brand_ptr = (unsigned int*) brand; + __get_cpuid(0x80000002, &brand_ptr[0], &brand_ptr[1], &brand_ptr[2], &brand_ptr[3]); + __get_cpuid(0x80000003, &brand_ptr[4], &brand_ptr[5], &brand_ptr[6], &brand_ptr[7]); + __get_cpuid(0x80000004, &brand_ptr[8], &brand_ptr[9], &brand_ptr[10], &brand_ptr[11]); + brand[48] = '\0'; + } + } + + // CPU Version Info (CPUID Leaf 1) + if (!__get_cpuid(1, &eax, &ebx, &ecx, &edx)) { + return false; + } + + int32_t family = (eax >> 8) & 0xF; + int32_t model = (eax >> 4) & 0xF; + int32_t stepping = eax & 0xF; + int32_t xfamily = (eax >> 20) & 0xFF; + + // https://github.com/anrieff/libcpuid/blob/2e4456ae0165db3155da2e8fba92afd5c090ca1b/libcpuid/cpuid_main.c#L1112 + int32_t ext_family = __builtin_expect(family < 0xF && ffStrbufEqualS(&cpu->vendor, "AuthenticAMD"), false) + ? family + : family + xfamily; + + int32_t xmodel = (eax >> 16) & 0xF; + int32_t ext_model = model + (xmodel << 4); + + const struct match_entry_t* matchtable = NULL; + uint32_t count = 0; + + if (ffStrbufEqualS(&cpu->vendor, "GenuineIntel")) { + matchtable = cpudb_intel; + count = ARRAY_SIZE(cpudb_intel); + } else if (ffStrbufEqualS(&cpu->vendor, "AuthenticAMD")) { + matchtable = cpudb_amd; + count = ARRAY_SIZE(cpudb_amd); + } else if (ffStrbufEqualS(&cpu->vendor, "CentaurHauls")) { + matchtable = cpudb_centaur; + count = ARRAY_SIZE(cpudb_centaur); + } else { + return false; + } + + const FFCPUX86MatchEntry* bestEntry = NULL; + int32_t bestScore = -1; + + for (uint32_t i = 0; i < count; i++) { + int score = 0; + const FFCPUX86MatchEntry* entry = &matchtable[i]; + + if (entry->family != family) { + continue; + } + + if (entry->model == model) { + score += 2; + } else if (entry->model != -1) { + continue; + } + + if (entry->stepping == stepping) { + score += 2; + } else if (entry->stepping != -1) { + continue; + } + + if (entry->ext_family == ext_family) { + score += 2; + } else if (entry->ext_family != -1) { + continue; + } + + if (entry->ext_model == ext_model) { + score += 2; + } else if (entry->ext_model != -1) { + continue; + } + + if (entry->brand.pattern[0] != '\0') { + if (match_brand_pattern(entry->brand.pattern, brand)) { + score += entry->brand.score; + } else { + continue; + } + } + + if (score > bestScore) { + bestScore = score; + bestEntry = entry; + } + } + + if (bestEntry && bestScore > 0) { + cpu->codeName = bestEntry->name; + cpu->technology = bestEntry->technology; + return true; + } + + return false; +} + +#endif diff --git a/src/modules/cpu/cpu.c b/src/modules/cpu/cpu.c index 0d3803af31..196b9e4533 100644 --- a/src/modules/cpu/cpu.c +++ b/src/modules/cpu/cpu.c @@ -102,6 +102,10 @@ bool ffPrintCPU(FFCPUOptions* options) { FF_ARG(cpu.packages, "packages"), FF_ARG(cpu.march, "march"), FF_ARG(cpu.numaNodes, "numa-nodes"), + #if __i386__ || __x86_64__ + FF_ARG(cpu.codeName, "code-name"), + FF_ARG(cpu.technology, "technology"), + #endif })); } success = true; @@ -214,6 +218,20 @@ bool ffGenerateCPUJsonResult(FFCPUOptions* options, yyjson_mut_doc* doc, yyjson_ yyjson_mut_obj_add_null(doc, obj, "numaNodes"); } + #if __i386__ || __x86_64__ + if (cpu.codeName) { + yyjson_mut_obj_add_str(doc, obj, "codeName", cpu.codeName); + } else { + yyjson_mut_obj_add_null(doc, obj, "codeName"); + } + + if (cpu.technology) { + yyjson_mut_obj_add_str(doc, obj, "technology", cpu.technology); + } else { + yyjson_mut_obj_add_null(doc, obj, "technology"); + } + #endif + success = true; } @@ -258,5 +276,9 @@ FFModuleBaseInfo ffCPUModuleInfo = { { "Processor package count", "packages" }, { "CPU microarchitecture", "march" }, { "NUMA node count", "numa-nodes" }, + #if __i386__ || __x86_64__ + { "CPU code name", "code-name" }, + { "CPU technology", "technology" }, + #endif })) }; From 8ee08d0067727f65371177eb56fc60aa980dd61b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E6=9D=8E=E9=80=9A=E6=B4=B2?= Date: Sun, 7 Jun 2026 16:40:40 +0800 Subject: [PATCH 06/19] CI: don't run heavy tests if the light one failed --- .github/workflows/ci.yml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index fc0c432b07..248c5e4ce5 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -9,6 +9,7 @@ jobs: uses: ./.github/workflows/build-spellcheck.yml no-features-test: + needs: spellcheck name: No-features-test permissions: security-events: write @@ -17,6 +18,7 @@ jobs: secrets: inherit linux-hosts: + needs: no-features-test name: Linux-${{ matrix.arch }} permissions: security-events: write @@ -35,6 +37,7 @@ jobs: secrets: inherit linux-i686: + needs: no-features-test name: Linux-i686 permissions: security-events: write @@ -43,6 +46,7 @@ jobs: secrets: inherit linux-armv7l: + needs: no-features-test name: Linux-armv7l permissions: security-events: write @@ -51,6 +55,7 @@ jobs: secrets: inherit linux-armv6l: + needs: no-features-test name: Linux-armv6l permissions: security-events: write @@ -59,6 +64,7 @@ jobs: secrets: inherit linux-vms: + needs: no-features-test name: Linux-${{ matrix.arch }} permissions: security-events: write @@ -75,11 +81,13 @@ jobs: secrets: inherit musl-amd64: + needs: no-features-test name: Musl-amd64 uses: ./.github/workflows/build-musl-amd64.yml secrets: inherit macos-hosts: + needs: no-features-test name: macOS-${{ matrix.arch }} permissions: security-events: write @@ -98,16 +106,19 @@ jobs: secrets: inherit omnios-amd64: + needs: no-features-test name: OmniOS-amd64 uses: ./.github/workflows/build-omnios-amd64.yml secrets: inherit solaris-amd64: + needs: no-features-test name: Solaris-amd64 uses: ./.github/workflows/build-solaris-amd64.yml secrets: inherit freebsd-amd64: + needs: no-features-test name: FreeBSD-amd64 permissions: security-events: write @@ -116,6 +127,7 @@ jobs: secrets: inherit openbsd-amd64: + needs: no-features-test name: OpenBSD-amd64 permissions: security-events: write @@ -124,6 +136,7 @@ jobs: secrets: inherit netbsd-amd64: + needs: no-features-test name: NetBSD-amd64 permissions: security-events: write @@ -132,6 +145,7 @@ jobs: secrets: inherit dragonfly-amd64: + needs: no-features-test name: DragonFly-amd64 permissions: security-events: write @@ -140,6 +154,7 @@ jobs: secrets: inherit haiku-amd64: + needs: no-features-test name: Haiku-amd64 permissions: security-events: write @@ -148,6 +163,7 @@ jobs: secrets: inherit windows-hosts: + needs: no-features-test name: Windows-${{ matrix.arch }} permissions: security-events: write From 8f266eb2a7088c10c74237417b9db75889ab1046 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E6=9D=8E=E9=80=9A=E6=B4=B2?= Date: Sun, 7 Jun 2026 16:41:59 +0800 Subject: [PATCH 07/19] Chore: don't check spelling in cpu_x86.c --- .codespellrc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.codespellrc b/.codespellrc index 48fa44238a..e8a7597eb3 100644 --- a/.codespellrc +++ b/.codespellrc @@ -1,5 +1,5 @@ [codespell] check-filenames = builtin = clear,rare,usage,informal -skip = */.git,*/cmake-build-*,*/.idea,*/completions,*/presets,*/screenshots,*/tests,*/3rdparty,*/logo/ascii,./src/detection/gpu/asahi_drm.h +skip = */.git,*/cmake-build-*,*/.idea,*/completions,*/presets,*/screenshots,*/tests,*/3rdparty,*/logo/ascii,./src/detection/gpu/asahi_drm.h,./src/detection/cpu/cpu_x86.c ignore-words-list = iterm,compiletime,unknwn,pengwin,siduction,master,slave,sur,doas,conexant,ags,bu From f09aebecd54db326f362942fa5fafce2eef9b5c2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E6=9D=8E=E9=80=9A=E6=B4=B2?= Date: Sun, 7 Jun 2026 16:48:15 +0800 Subject: [PATCH 08/19] CPU (X86): updates comments --- src/detection/cpu/cpu_x86.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/detection/cpu/cpu_x86.c b/src/detection/cpu/cpu_x86.c index b5e61e05b5..c79b817c6e 100644 --- a/src/detection/cpu/cpu_x86.c +++ b/src/detection/cpu/cpu_x86.c @@ -1153,7 +1153,7 @@ const struct match_entry_t cpudb_amd[] = { /********************************************************************************** */ -// https://github.com/anrieff/libcpuid/blob/2e4456ae0165db3155da2e8fba92afd5c090ca1b/libcpuid/recog_centaur.c +// https://github.com/anrieff/libcpuid/blob/ff6b7500351293259ca808783ee81e8ab5b7c0cb/libcpuid/recog_centaur.c /* * Copyright 2023 Veselin Georgiev, * anrieffNOSPAM @ mgail_DOT.com (convert to gmail) From e946861eb0f1c95dd8a02fcd45052f1286a095d1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E6=9D=8E=E9=80=9A=E6=B4=B2?= Date: Sun, 7 Jun 2026 23:13:44 +0800 Subject: [PATCH 09/19] Codec (Windows): fixes compatibility of Win 8.1 --- src/detection/codec/codec_windows.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/detection/codec/codec_windows.cpp b/src/detection/codec/codec_windows.cpp index df01a63789..9e2183959a 100644 --- a/src/detection/codec/codec_windows.cpp +++ b/src/detection/codec/codec_windows.cpp @@ -408,13 +408,13 @@ const char* detectD3d11va(FFCodecOptions* options, FFlist* result /*list of FFCo FF_LIBRARY_LOAD_SYMBOL_MESSAGE(d3d11, D3D11CreateDevice) FF_LIBRARY_LOAD_MESSAGE(mfplat, "mfplat" FF_LIBRARY_EXTENSION, 1) FF_LIBRARY_LOAD_SYMBOL_MESSAGE(mfplat, MFCreateAttributes) - FF_LIBRARY_LOAD_SYMBOL_MESSAGE(mfplat, MFTEnum2) + FF_LIBRARY_LOAD_SYMBOL_LAZY(mfplat, MFTEnum2) // Not available on Windows 8.1 ffEnumHardwareAdapters(factory, [&](IDXGIAdapter1* adapter, const DXGI_ADAPTER_DESC1& desc) { FFCodecType decoders = (options->showType & FF_CODEC_SHOW_TYPE_DECODER) ? ffDetectD3d11vaDecoders(adapter, ffD3D11CreateDevice) : FF_CODEC_TYPE_NONE; - FFCodecType encoders = (options->showType & FF_CODEC_SHOW_TYPE_ENCODER) + FFCodecType encoders = ffMFTEnum2 && (options->showType & FF_CODEC_SHOW_TYPE_ENCODER) ? ffDetectD3d11MftEncoders(desc.AdapterLuid, ffMFCreateAttributes, ffMFTEnum2) : FF_CODEC_TYPE_NONE; @@ -426,7 +426,7 @@ const char* detectD3d11va(FFCodecOptions* options, FFlist* result /*list of FFCo ffStrbufInitWS(&gpuResult->gpu, desc.Description); gpuResult->decoders = decoders; gpuResult->encoders = encoders; - gpuResult->platformApi = "D3D11VA+MFT"; + gpuResult->platformApi = ffMFTEnum2 ? "D3D11VA+MFT" : "D3D11VA"; }); return nullptr; From 5cd4316f989870ee27c959cd2a8f6c7f87ac0eaf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E6=9D=8E=E9=80=9A=E6=B4=B2?= Date: Mon, 8 Jun 2026 00:27:47 +0800 Subject: [PATCH 10/19] CPU (X86): uses normalized cpu brand name for pattern matching --- src/detection/cpu/cpu_x86.c | 28 ++++++++-------------------- 1 file changed, 8 insertions(+), 20 deletions(-) diff --git a/src/detection/cpu/cpu_x86.c b/src/detection/cpu/cpu_x86.c index c79b817c6e..573fc31db0 100644 --- a/src/detection/cpu/cpu_x86.c +++ b/src/detection/cpu/cpu_x86.c @@ -1284,25 +1284,13 @@ bool ffCPUDetectX86Specific(FFCPUResult* cpu) { return false; } - ffStrbufClear(&cpu->vendor); - ffStrbufEnsureFixedLengthFree(&cpu->vendor, 12); - memcpy(cpu->vendor.chars + 0, &ebx, 4); - memcpy(cpu->vendor.chars + 4, &edx, 4); - memcpy(cpu->vendor.chars + 8, &ecx, 4); - cpu->vendor.chars[12] = '\0'; - cpu->vendor.length = 12; - - // Brand String (CPUID Leaves 0x80000002 - 0x80000004) - char brand[49] = {}; - unsigned int ext_eax; - if (__get_cpuid(0x80000000, &ext_eax, &ebx, &ecx, &edx)) { - if (ext_eax >= 0x80000004) { - unsigned int* brand_ptr = (unsigned int*) brand; - __get_cpuid(0x80000002, &brand_ptr[0], &brand_ptr[1], &brand_ptr[2], &brand_ptr[3]); - __get_cpuid(0x80000003, &brand_ptr[4], &brand_ptr[5], &brand_ptr[6], &brand_ptr[7]); - __get_cpuid(0x80000004, &brand_ptr[8], &brand_ptr[9], &brand_ptr[10], &brand_ptr[11]); - brand[48] = '\0'; - } + if (!cpu->vendor.length) { + ffStrbufEnsureFixedLengthFree(&cpu->vendor, 12); + memcpy(cpu->vendor.chars + 0, &ebx, 4); + memcpy(cpu->vendor.chars + 4, &edx, 4); + memcpy(cpu->vendor.chars + 8, &ecx, 4); + cpu->vendor.chars[12] = '\0'; + cpu->vendor.length = 12; } // CPU Version Info (CPUID Leaf 1) @@ -1375,7 +1363,7 @@ bool ffCPUDetectX86Specific(FFCPUResult* cpu) { } if (entry->brand.pattern[0] != '\0') { - if (match_brand_pattern(entry->brand.pattern, brand)) { + if (match_brand_pattern(entry->brand.pattern, cpu->name.chars)) { score += entry->brand.score; } else { continue; From 70061625f73fae24292cfeda37e78eae713caf5c Mon Sep 17 00:00:00 2001 From: Carter Li Date: Mon, 8 Jun 2026 10:37:11 +0800 Subject: [PATCH 11/19] Chore: adds `FF_A_COLD` --- src/common/attributes.h | 1 + src/fastfetch.c | 16 ++++++++++++++-- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/src/common/attributes.h b/src/common/attributes.h index ff1e66067b..a7b964c4d4 100644 --- a/src/common/attributes.h +++ b/src/common/attributes.h @@ -17,3 +17,4 @@ #define FF_A_PACKED __attribute__((__packed__)) #define FF_A_WEAK_IMPORT __attribute__((__weak_import__)) #define FF_A_ALWAYS_INLINE __attribute__((__always_inline__)) +#define FF_A_COLD __attribute__((__cold__)) diff --git a/src/fastfetch.c b/src/fastfetch.c index dc5c1797d8..a5e76d1a05 100644 --- a/src/fastfetch.c +++ b/src/fastfetch.c @@ -15,6 +15,7 @@ #include #include +FF_A_COLD static void printCommandFormatHelpJson(void) { yyjson_mut_doc* doc = yyjson_mut_doc_new(NULL); yyjson_mut_val* root = yyjson_mut_obj(doc); @@ -49,6 +50,7 @@ static void printCommandFormatHelpJson(void) { yyjson_mut_doc_free(doc); } +FF_A_COLD static void printCommandFormatHelp(const char* command) { FF_STRBUF_AUTO_DESTROY type = ffStrbufCreateNS((uint32_t) (strlen(command) - strlen("-format")), command); ffStrbufLowerCase(&type); @@ -85,6 +87,7 @@ static void printCommandFormatHelp(const char* command) { fprintf(stderr, "Error: Module '%s' is not supported\n", type.chars); } +FF_A_COLD static void printFullHelp() { fputs("Fastfetch is a neofetch-like tool for fetching system information and displaying them in a pretty way\n\n", stdout); if (!instance.config.display.pipe) { @@ -191,6 +194,7 @@ For detailed information on logo options, module configuration, and formatting, https://github.com/fastfetch-cli/fastfetch/wiki/Configuration"); } +FF_A_COLD static bool printSpecificCommandHelp(const char* command) { yyjson_doc* doc = yyjson_read(FASTFETCH_DATATEXT_JSON_HELP, strlen(FASTFETCH_DATATEXT_JSON_HELP), YYJSON_READ_NOFLAG); assert(doc); @@ -301,6 +305,7 @@ static bool printSpecificCommandHelp(const char* command) { return false; } +FF_A_COLD static void printCommandHelp(const char* command) { if (command == NULL) { printFullHelp(); @@ -313,6 +318,7 @@ static void printCommandHelp(const char* command) { } } +FF_A_COLD static void listAvailablePresets(bool pretty) { FF_LIST_FOR_EACH (FFstrbuf, path, instance.state.platform.dataDirs) { ffStrbufAppendS(path, "fastfetch/presets/"); @@ -327,6 +333,7 @@ static void listAvailablePresets(bool pretty) { } } +FF_A_COLD static void listAvailableLogos(void) { FF_LIST_FOR_EACH (FFstrbuf, path, instance.state.platform.dataDirs) { ffStrbufAppendS(path, "fastfetch/logos/"); @@ -334,6 +341,7 @@ static void listAvailableLogos(void) { } } +FF_A_COLD static void listConfigPaths(void) { FF_LIST_FOR_EACH (FFstrbuf, folder, instance.state.platform.configDirs) { bool exists = false; @@ -345,6 +353,7 @@ static void listConfigPaths(void) { } } +FF_A_COLD static void listDataPaths(void) { FF_LIST_FOR_EACH (FFstrbuf, folder, instance.state.platform.dataDirs) { ffStrbufAppendS(folder, "fastfetch/"); @@ -352,6 +361,7 @@ static void listDataPaths(void) { } } +FF_A_COLD static void listModules(bool pretty) { unsigned count = 0; for (int i = 0; i <= 'Z' - 'A'; ++i) { @@ -415,6 +425,7 @@ static bool parseJsoncFile(FFdata* data, const char* path, yyjson_read_flag flg) return true; } +FF_A_COLD static void generateConfigFile(FFdata* data, bool force, const char* filePath, bool fullConfig) { if (data->resultDoc) { fprintf(stderr, "Error: duplicated `--gen-config` or `--format json` flags found\n"); @@ -552,6 +563,7 @@ static void optionParseConfigFile(FFdata* data, const char* key, const char* val exit(414); } +FF_A_COLD static void printVersion() { FFVersionResult* result = &ffVersionResult; printf("%s %s%s%s (%s)\n", result->projectName, result->version, result->versionTweak, result->debugMode ? "-debug" : "", result->architecture); @@ -572,8 +584,7 @@ static void parseCommand(FFdata* data, char* key, char* value) { if (ffStrEqualsIgnCase(key, "-h") || ffStrEqualsIgnCase(key, "--help")) { printCommandHelp(value); exit(0); - } - if (ffStrEqualsIgnCase(key, "--help-raw")) { + } else if (ffStrEqualsIgnCase(key, "--help-raw")) { puts(FASTFETCH_DATATEXT_JSON_HELP); exit(0); } else if (ffStrEqualsIgnCase(key, "-v") || ffStrEqualsIgnCase(key, "--version")) { @@ -792,6 +803,7 @@ static void run(FFdata* data) { } } +FF_A_COLD static void writeConfigFile(FFdata* data) { const FFstrbuf* filename = &data->genConfigPath; From a720e1f945e68fd80b3781ff5e1b96b96871b3d4 Mon Sep 17 00:00:00 2001 From: Carter Li Date: Mon, 8 Jun 2026 10:37:58 +0800 Subject: [PATCH 12/19] Fastfetch (Windows): moves `SetConsoleMode` and `SetConsoleOutputCP` to the start of process Fixes #2383 --- src/common/impl/init.c | 36 ++++++++++++++++++++---------------- 1 file changed, 20 insertions(+), 16 deletions(-) diff --git a/src/common/impl/init.c b/src/common/impl/init.c index f0fc0a2f32..b24660eeb1 100644 --- a/src/common/impl/init.c +++ b/src/common/impl/init.c @@ -46,10 +46,30 @@ static void defaultConfig(void) { ffOptionsInitDisplay(&instance.config.display); } +#ifdef _WIN32 +static volatile UINT oldCp = CP_UTF8; +void resetConsoleCP(void) { + if (oldCp != CP_UTF8) { + SetConsoleOutputCP(oldCp); + } +} +#endif + void ffInitInstance(void) { #ifdef _WIN32 // https://learn.microsoft.com/en-us/cpp/c-runtime-library/reference/setlocale-wsetlocale?source=recommendat> setlocale(LC_ALL, ".UTF8"); + + HANDLE hStdout = GetStdHandle(STD_OUTPUT_HANDLE); + DWORD mode = 0; + if (GetConsoleMode(hStdout, &mode)) { + SetConsoleMode(hStdout, mode | ENABLE_PROCESSED_OUTPUT | ENABLE_VIRTUAL_TERMINAL_PROCESSING); + oldCp = GetConsoleOutputCP(); + if (oldCp != CP_UTF8) { + SetConsoleOutputCP(CP_UTF8); + atexit(resetConsoleCP); + } + } #else // Never use `setlocale(LC_ALL, "")` setlocale(LC_TIME, ""); @@ -61,9 +81,6 @@ void ffInitInstance(void) { static volatile bool ffDisableLinewrap = false; static volatile bool ffHideCursor = false; -#ifdef _WIN32 -static volatile UINT oldCp = CP_UTF8; -#endif static void resetConsole(void) { if (ffDisableLinewrap) { @@ -80,10 +97,6 @@ static void resetConsole(void) { #if defined(_WIN32) fflush(stdout); - - if (oldCp != CP_UTF8) { - SetConsoleOutputCP(oldCp); - } #endif } @@ -111,15 +124,6 @@ void ffStart(void) { setvbuf(stdout, NULL, _IOFBF, 4096); } SetConsoleCtrlHandler(consoleHandler, TRUE); - HANDLE hStdout = GetStdHandle(STD_OUTPUT_HANDLE); - DWORD mode = 0; - if (GetConsoleMode(hStdout, &mode)) { - SetConsoleMode(hStdout, mode | ENABLE_PROCESSED_OUTPUT | ENABLE_VIRTUAL_TERMINAL_PROCESSING); - oldCp = GetConsoleOutputCP(); - if (oldCp != CP_UTF8) { - SetConsoleOutputCP(CP_UTF8); - } - } #else if (instance.config.display.noBuffer) { setvbuf(stdout, NULL, _IONBF, 0); From 3ec7e94b47924dbbd7c56f1e543c220fa295a104 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E6=9D=8E=E9=80=9A=E6=B4=B2?= Date: Mon, 8 Jun 2026 18:09:32 +0800 Subject: [PATCH 13/19] CPU (Windows): uses a better way to fetch core types --- src/detection/cpu/cpu_windows.c | 59 +++++++++++++++++---------------- 1 file changed, 30 insertions(+), 29 deletions(-) diff --git a/src/detection/cpu/cpu_windows.c b/src/detection/cpu/cpu_windows.c index 86edce912e..078ba0b837 100644 --- a/src/detection/cpu/cpu_windows.c +++ b/src/detection/cpu/cpu_windows.c @@ -216,7 +216,21 @@ static const char* detectMaxSpeedBySmbios(FFCPUResult* cpu) { return NULL; } -static const char* detectNCores(FFCPUResult* cpu) { +static uint32_t getNumLogicalCores(const SYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX* ptr) { + uint32_t num = 0; + for (uint32_t i = 0; i < ptr->Processor.GroupCount; ++i) { + num += (uint32_t) +#if _WIN64 + __builtin_popcountll +#else + __builtin_popcountl +#endif + (ptr->Processor.GroupMask[i].Mask); + } + return num; +} + +static const char* detectNCores(const FFCPUOptions* options, FFCPUResult* cpu) { LOGICAL_PROCESSOR_RELATIONSHIP lpr = RelationAll; ULONG length = 0; NtQuerySystemInformationEx(SystemLogicalProcessorAndGroupInformation, &lpr, sizeof(lpr), NULL, 0, &length); @@ -242,6 +256,19 @@ static const char* detectNCores(FFCPUResult* cpu) { } } else if (ptr->Relationship == RelationProcessorCore) { ++cpu->coresPhysical; + + if (options->showPeCoreCount) { + for (uint32_t i = 0; i < ARRAY_SIZE(cpu->coreTypes); ++i) { + if (ptr->Processor.EfficiencyClass + 1 == cpu->coreTypes[i].freq) { + cpu->coreTypes[i].count += getNumLogicalCores(ptr); + break; + } else if (cpu->coreTypes[i].freq == 0) { + cpu->coreTypes[i].freq = ptr->Processor.EfficiencyClass + 1; + cpu->coreTypes[i].count += getNumLogicalCores(ptr); + break; + } + } + } } else if (ptr->Relationship == RelationProcessorPackage) { ++cpu->packages; } else if (ptr->Relationship == RelationNumaNode) { @@ -258,7 +285,7 @@ static const char* detectByRegistry(FFCPUResult* cpu) { return "ffRegOpenKeyForRead(HKEY_LOCAL_MACHINE, L\"HARDWARE\\DESCRIPTION\\System\\CentralProcessor\\0\", &hKey, NULL) failed"; } - if (ffRegReadValues(hKey, 3, (FFRegValueArg[]) { + if (ffRegReadValues(hKey, 3, (FFRegValueArg[]){ FF_ARG(cpu->name, L"ProcessorNameString"), FF_ARG(cpu->vendor, L"VendorIdentifier"), FF_ARG(cpu->frequencyBase, L"~MHz"), @@ -272,31 +299,8 @@ static const char* detectByRegistry(FFCPUResult* cpu) { return NULL; } -static const char* detectCoreTypes(FFCPUResult* cpu) { - FF_AUTO_FREE PROCESSOR_POWER_INFORMATION* pinfo = calloc(cpu->coresLogical, sizeof(PROCESSOR_POWER_INFORMATION)); - if (!NT_SUCCESS(NtPowerInformation(ProcessorInformation, NULL, 0, pinfo, (ULONG) sizeof(PROCESSOR_POWER_INFORMATION) * cpu->coresLogical))) { - return "NtPowerInformation(ProcessorInformation, NULL, 0, pinfo, size) failed"; - } - - for (uint32_t icore = 0; icore < cpu->coresLogical && pinfo[icore].MhzLimit; ++icore) { - uint32_t ifreq = 0; - while (cpu->coreTypes[ifreq].freq != pinfo[icore].MhzLimit && cpu->coreTypes[ifreq].freq > 0) { - ++ifreq; - } - if (cpu->coreTypes[ifreq].freq == 0) { - cpu->coreTypes[ifreq].freq = pinfo[icore].MhzLimit; - } - ++cpu->coreTypes[ifreq].count; - } - - if (cpu->frequencyBase == 0) { - cpu->frequencyBase = pinfo->MaxMhz; - } - return NULL; -} - const char* ffDetectCPUImpl(const FFCPUOptions* options, FFCPUResult* cpu) { - detectNCores(cpu); + detectNCores(options, cpu); const char* error = detectByRegistry(cpu); if (error) { @@ -304,9 +308,6 @@ const char* ffDetectCPUImpl(const FFCPUOptions* options, FFCPUResult* cpu) { } ffCPUDetectByCpuid(cpu); - if (options->showPeCoreCount) { - detectCoreTypes(cpu); - } if (cpu->frequencyMax == 0) { detectMaxSpeedBySmbios(cpu); From 35c2f8c9243957c26bf47dea79c3eeb4b3f2b2f9 Mon Sep 17 00:00:00 2001 From: Carter Li Date: Tue, 9 Jun 2026 13:09:58 +0800 Subject: [PATCH 14/19] CPU (Linux): fixes physical core detection on non-x86 --- src/detection/cpu/cpu_linux.c | 23 +++++++++-------------- 1 file changed, 9 insertions(+), 14 deletions(-) diff --git a/src/detection/cpu/cpu_linux.c b/src/detection/cpu/cpu_linux.c index b228d5230b..ba1796784c 100644 --- a/src/detection/cpu/cpu_linux.c +++ b/src/detection/cpu/cpu_linux.c @@ -773,6 +773,7 @@ static const char* detectPhysicalCores(FFCPUResult* cpu) { FF_AUTO_CLOSE_DIR DIR* dir = fdopendir(dfd); if (!dir) { + close(dfd); return "fdopendir(dfd) failed"; } @@ -785,7 +786,7 @@ static const char* detectPhysicalCores(FFCPUResult* cpu) { continue; } - FF_AUTO_CLOSE_FD int cpuxfd = openat(dirfd(dir), entry->d_name, O_RDONLY | O_DIRECTORY); + FF_AUTO_CLOSE_FD int cpuxfd = openat(dirfd(dir), entry->d_name, O_RDONLY | O_DIRECTORY | O_CLOEXEC); if (cpuxfd < 0) { continue; } @@ -801,22 +802,23 @@ static const char* detectPhysicalCores(FFCPUResult* cpu) { unsigned long long id = strtoul(buf, NULL, 10); if (__builtin_expect(id > 64, false)) { // Do 129-socket boards exist? pkgHigh |= 1ULL << (id - 64); - } else { + } else if (__builtin_expect(id <= 64, true)) { pkgLow |= 1ULL << id; } } // Check if the directory contains a file named "topology/core_cpus_list" - // that lists the physical cores in the package. + // that lists the logical cores in the same physical core. len = ffReadFileDataRelative(cpuxfd, "topology/core_cpus_list", sizeof(buf) - 1, buf); if (len > 0) { - buf[len] = '\0'; // low-high or low + buf[len] = '\0'; // low[-high, low-high, ...] - for (const char* p = buf; *p;) { char* pend; - uint32_t coreId = (uint32_t) strtoul(p, &pend, 10); - if (pend == p) { + // We assume that the different physical cores exposes different logical core ids, + // so that the first `low` is always different between different physical cores. + uint32_t coreId = (uint32_t) strtoul(buf, &pend, 10); + if (pend == buf) { break; } @@ -831,13 +833,6 @@ static const char* detectPhysicalCores(FFCPUResult* cpu) { if (!found) { *FF_LIST_ADD(uint32_t, cpuList) = coreId; } - - p = strchr(pend, ','); - if (!p) { - break; - } - ++p; - } } } From 09e28451ec0131570bf291f7abd12ee973073427 Mon Sep 17 00:00:00 2001 From: Carter Li Date: Tue, 9 Jun 2026 13:38:49 +0800 Subject: [PATCH 15/19] CPU (Linux): simplifies code of frequency detection --- src/detection/cpu/cpu_linux.c | 77 +++++++++++++---------------------- 1 file changed, 28 insertions(+), 49 deletions(-) diff --git a/src/detection/cpu/cpu_linux.c b/src/detection/cpu/cpu_linux.c index ba1796784c..6f792c54bc 100644 --- a/src/detection/cpu/cpu_linux.c +++ b/src/detection/cpu/cpu_linux.c @@ -619,19 +619,14 @@ static const char* parseCpuInfo( return NULL; } -static uint32_t getFrequency(FFstrbuf* basePath, const char* cpuinfoFileName, const char* scalingFileName, FFstrbuf* buffer) { - uint32_t baseLen = basePath->length; - ffStrbufAppendS(basePath, cpuinfoFileName); - bool ok = ffReadFileBuffer(basePath->chars, buffer); - ffStrbufSubstrBefore(basePath, baseLen); +static uint32_t getFrequency(int policyFd, const char* cpuinfoFileName, const char* scalingFileName, FFstrbuf* buffer) { + bool ok = ffReadFileBufferRelative(policyFd, cpuinfoFileName, buffer); if (ok) { return (uint32_t) (ffStrbufToUInt(buffer, 0) / 1000); } if (scalingFileName) { - ffStrbufAppendS(basePath, scalingFileName); - ok = ffReadFileBuffer(basePath->chars, buffer); - ffStrbufSubstrBefore(basePath, baseLen); + ok = ffReadFileBufferRelative(policyFd, scalingFileName, buffer); if (ok) { return (uint32_t) (ffStrbufToUInt(buffer, 0) / 1000); } @@ -640,55 +635,38 @@ static uint32_t getFrequency(FFstrbuf* basePath, const char* cpuinfoFileName, co return 0; } -static uint8_t getNumCores(FFstrbuf* basePath, FFstrbuf* buffer) { - uint32_t baseLen = basePath->length; - ffStrbufAppendS(basePath, "/affected_cpus"); - bool ok = ffReadFileBuffer(basePath->chars, buffer); - ffStrbufSubstrBefore(basePath, baseLen); - if (ok) { - return (uint8_t) (ffStrbufCountC(buffer, ' ') + 1); - } - - ffStrbufAppendS(basePath, "/related_cpus"); - ok = ffReadFileBuffer(basePath->chars, buffer); - ffStrbufSubstrBefore(basePath, baseLen); - if (ok) { - return (uint8_t) (ffStrbufCountC(buffer, ' ') + 1); - } - - return 0; -} - static bool detectFrequency(FFCPUResult* cpu, const FFCPUOptions* options) { - FF_STRBUF_AUTO_DESTROY path = ffStrbufCreateS("/sys/devices/system/cpu/cpufreq/"); - FF_AUTO_CLOSE_DIR DIR* dir = opendir(path.chars); + const char* basePath = "/sys/devices/system/cpu/cpufreq/"; + FF_AUTO_CLOSE_DIR DIR* dir = opendir(basePath); if (!dir) { return false; } + int freqFd = dirfd(dir); FF_STRBUF_AUTO_DESTROY buffer = ffStrbufCreate(); - uint32_t baseLen = path.length; struct dirent* entry; while ((entry = readdir(dir)) != NULL) { if (ffStrStartsWith(entry->d_name, "policy") && ffCharIsDigit(entry->d_name[strlen("policy")])) { - ffStrbufAppendS(&path, entry->d_name); + FF_AUTO_CLOSE_FD int policyFd = openat(freqFd, entry->d_name, O_RDONLY | O_DIRECTORY | O_CLOEXEC | O_PATH); + if (policyFd < 0) { + continue; + } - uint32_t fmax = getFrequency(&path, "/cpuinfo_max_freq", "/scaling_max_freq", &buffer); + uint32_t fmax = getFrequency(policyFd, "cpuinfo_max_freq", "scaling_max_freq", &buffer); if (fmax == 0) { continue; } if (cpu->frequencyMax >= fmax) { if (!options->showPeCoreCount) { - ffStrbufSubstrBefore(&path, baseLen); continue; } } else { cpu->frequencyMax = fmax; } - uint32_t fbase = getFrequency(&path, "/base_frequency", NULL, &buffer); + uint32_t fbase = getFrequency(policyFd, "base_frequency", NULL, &buffer); if (fbase > 0) { cpu->frequencyBase = cpu->frequencyBase > fbase ? cpu->frequencyBase : fbase; } @@ -702,9 +680,10 @@ static bool detectFrequency(FFCPUResult* cpu, const FFCPUOptions* options) { if (cpu->coreTypes[ifreq].freq == 0) { cpu->coreTypes[ifreq].freq = freq; } - cpu->coreTypes[ifreq].count += getNumCores(&path, &buffer); + if (ffReadFileBufferRelative(policyFd, "affected_cpus", &buffer)) { + cpu->coreTypes[ifreq].count += ffStrbufCountC(&buffer, ' ') + 1; + } } - ffStrbufSubstrBefore(&path, baseLen); } } return true; @@ -814,25 +793,25 @@ static const char* detectPhysicalCores(FFCPUResult* cpu) { if (len > 0) { buf[len] = '\0'; // low[-high, low-high, ...] - char* pend; + char* pend; // We assume that the different physical cores exposes different logical core ids, // so that the first `low` is always different between different physical cores. uint32_t coreId = (uint32_t) strtoul(buf, &pend, 10); if (pend == buf) { - break; - } + break; + } - bool found = false; - FF_LIST_FOR_EACH (uint32_t, id, cpuList) { - if (*id == coreId) { - // This core is already counted - found = true; - break; - } - } - if (!found) { - *FF_LIST_ADD(uint32_t, cpuList) = coreId; + bool found = false; + FF_LIST_FOR_EACH (uint32_t, id, cpuList) { + if (*id == coreId) { + // This core is already counted + found = true; + break; } + } + if (!found) { + *FF_LIST_ADD(uint32_t, cpuList) = coreId; + } } } From 43301afc47eae572dd9a089dca4a4cddc82a40af Mon Sep 17 00:00:00 2001 From: Carter Li Date: Tue, 9 Jun 2026 14:04:54 +0800 Subject: [PATCH 16/19] CPU: enables `showPeCoreCount` by default --- src/modules/cpu/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/modules/cpu/cpu.c b/src/modules/cpu/cpu.c index 196b9e4533..57b7d1f33a 100644 --- a/src/modules/cpu/cpu.c +++ b/src/modules/cpu/cpu.c @@ -246,7 +246,7 @@ void ffInitCPUOptions(FFCPUOptions* options) { ffStrbufInit(&options->tempSensor); options->temp = false; options->tempConfig = (FFColorRangeConfig) { 60, 80 }; - options->showPeCoreCount = false; + options->showPeCoreCount = true; } void ffDestroyCPUOptions(FFCPUOptions* options) { From eb54c89b4a7e6270a8fedf81e762a54e38af8edf Mon Sep 17 00:00:00 2001 From: Carter Li Date: Tue, 9 Jun 2026 14:05:23 +0800 Subject: [PATCH 17/19] OS (macOS): adds the code name of macOS 27 --- src/detection/os/os_apple.m | 1 + 1 file changed, 1 insertion(+) diff --git a/src/detection/os/os_apple.m b/src/detection/os/os_apple.m index 2890fc31ab..570a723234 100644 --- a/src/detection/os/os_apple.m +++ b/src/detection/os/os_apple.m @@ -44,6 +44,7 @@ static bool detectOSCodeName(FFOSResult* os) switch (num) { + case 27: ffStrbufSetStatic(&os->codename, "Golden Gate"); return true; case 26: case 16: ffStrbufSetStatic(&os->codename, "Tahoe"); return true; case 15: ffStrbufSetStatic(&os->codename, "Sequoia"); return true; From 4594734b66a76e4e8f774c8031323bc57490ca4a Mon Sep 17 00:00:00 2001 From: Carter Li Date: Tue, 9 Jun 2026 16:07:56 +0800 Subject: [PATCH 18/19] CI (OpenBSD): updates OS version --- .github/workflows/build-openbsd-amd64.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/build-openbsd-amd64.yml b/.github/workflows/build-openbsd-amd64.yml index cae4cbb231..c879bc9bd0 100644 --- a/.github/workflows/build-openbsd-amd64.yml +++ b/.github/workflows/build-openbsd-amd64.yml @@ -20,7 +20,7 @@ jobs: architecture: x86-64 cpu_count: 4 shell: bash - version: '7.8' + version: '7.9' environment_variables: 'CMAKE_BUILD_TYPE' run: | uname -a From defc118cfacac567f999561947794b334362b27b Mon Sep 17 00:00:00 2001 From: ihpecvns Date: Wed, 10 Jun 2026 21:22:22 +0800 Subject: [PATCH 19/19] feat(terminalfont): add kmscon font detection Read kmscon's config file (found via --configdir in /proc//cmdline, falling back to /etc/kmscon/kmscon.conf) to extract font-name and font-size. Fixes #2393 --- .../terminalfont/terminalfont_linux.c | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/src/detection/terminalfont/terminalfont_linux.c b/src/detection/terminalfont/terminalfont_linux.c index bfc8959dce..6cd1d8bf61 100644 --- a/src/detection/terminalfont/terminalfont_linux.c +++ b/src/detection/terminalfont/terminalfont_linux.c @@ -483,6 +483,59 @@ static void detectHaikuTerminal(FFTerminalFontResult* terminalFont) { } #endif +static void detectKmscon(FFTerminalFontResult* terminalFont, const FFTerminalResult* terminal) { + FF_STRBUF_AUTO_DESTROY cmdline = ffStrbufCreate(); + FF_STRBUF_AUTO_DESTROY cmdlinePath = ffStrbufCreateF("/proc/%u/cmdline", terminal->pid); + if (!ffAppendFileBuffer(cmdlinePath.chars, &cmdline)) { + ffStrbufAppendF(&terminalFont->error, "Failed to open %s", cmdlinePath.chars); + return; + } + + // Search for --configdir in NUL-separated cmdline (safe: memmem/memchr, no strlen) + FF_STRBUF_AUTO_DESTROY configdir = ffStrbufCreate(); + const char* p = memmem(cmdline.chars, cmdline.length, "\0--configdir\0", sizeof("\0--configdir\0") - 1); + if (p) { + const char* val = p + sizeof("\0--configdir\0") - 1; + const char* end = cmdline.chars + cmdline.length; + if (val < end) { + const char* valEnd = memchr(val, '\0', (size_t)(end - val)); + if (valEnd && valEnd > val) + ffStrbufSetNS(&configdir, (uint32_t)(valEnd - val), val); + } + } + + // Build config file path — only accept absolute paths + FF_STRBUF_AUTO_DESTROY configPath = ffStrbufCreate(); + if (configdir.length > 0 && configdir.chars[0] == '/') { + ffStrbufAppendS(&configPath, configdir.chars); + ffStrbufAppendS(&configPath, "/kmscon.conf"); + } else { + ffStrbufAppendS(&configPath, FASTFETCH_TARGET_DIR_ETC "/kmscon/kmscon.conf"); + } + + FF_STRBUF_AUTO_DESTROY fontName = ffStrbufCreate(); + FF_STRBUF_AUTO_DESTROY fontSize = ffStrbufCreate(); + + if (!ffParsePropFileValues(configPath.chars, 2, (FFpropquery[]) { + { "font-name=", &fontName }, + { "font-size=", &fontSize }, + })) { + ffStrbufAppendF(&terminalFont->error, "Couldn't read kmscon config: %s", configPath.chars); + return; + } + + if (fontName.length == 0) { + ffStrbufAppendF(&terminalFont->error, "Couldn't find font-name in %s", configPath.chars); + return; + } + + if (fontSize.length == 0) { + ffStrbufSetStatic(&fontSize, "16"); + } + + ffFontInitValues(&terminalFont->font, fontName.chars, fontSize.chars); +} + bool #ifdef __ANDROID__ ffDetectTerminalFontPlatformLinux @@ -538,6 +591,8 @@ ffDetectTerminalFontPlatform detectFromConfigFile("termite/config", "font =", terminalFont); } else if (ffStrbufIgnCaseEqualS(&terminal->processName, "rxvt") || ffStrbufIgnCaseEqualS(&terminal->processName, "urxvt") || ffStrbufIgnCaseEqualS(&terminal->processName, "urxvtd")) { detectUrxvt(terminalFont); + } else if (ffStrbufIgnCaseEqualS(&terminal->processName, "kmscon")) { + detectKmscon(terminalFont, terminal); } else { return false; }