From 3c7b5b7371ff6c6c627d73712d80066fa1b117bc Mon Sep 17 00:00:00 2001
From: macabeus <bruno.macabeus@gmail.com>
Date: Mon, 22 Jun 2026 23:11:47 +0100
Subject: [PATCH] Add support for `R_ARM_V4BX`

---
 objdiff-core/src/arch/arm.rs       |  10 ++++++++++
 objdiff-core/tests/arch_arm.rs     |  16 ++++++++++++++++
 objdiff-core/tests/data/arm/v4bx.o | Bin 0 -> 644 bytes
 3 files changed, 26 insertions(+)
 create mode 100644 objdiff-core/tests/data/arm/v4bx.o

diff --git a/objdiff-core/src/arch/arm.rs b/objdiff-core/src/arch/arm.rs
index 35416c9f..184b26bc 100644
--- a/objdiff-core/src/arch/arm.rs
+++ b/objdiff-core/src/arch/arm.rs
@@ -343,6 +343,15 @@ impl Arch for ArchArm {
             // Handle ELF implicit relocations
             object::RelocationFlags::Elf { r_type } => {
                 if relocation.has_implicit_addend() {
+                    // R_ARM_V4BX marks a `bx` instruction so the linker can optionally
+                    // rewrite it for ARMv4 interworking. Drops the addend since it's meaningless.
+                    if r_type == elf::R_ARM_V4BX {
+                        return Ok(Some(RelocationOverride {
+                            target: RelocationOverrideTarget::Skip,
+                            addend: 0,
+                        }));
+                    }
+
                     let section_data = section.data()?;
                     let address = address as usize;
                     let addend = match r_type {
@@ -419,6 +428,7 @@ impl Arch for ArchArm {
                 elf::R_ARM_CALL => Some("R_ARM_CALL"),
                 elf::R_ARM_THM_PC11 => Some("R_ARM_THM_PC11"),
                 elf::R_ARM_THM_PC9 => Some("R_ARM_THM_PC9"),
+                elf::R_ARM_V4BX => Some("R_ARM_V4BX"),
                 _ => None,
             },
             _ => None,
diff --git a/objdiff-core/tests/arch_arm.rs b/objdiff-core/tests/arch_arm.rs
index 9c507e1d..37cc8386 100644
--- a/objdiff-core/tests/arch_arm.rs
+++ b/objdiff-core/tests/arch_arm.rs
@@ -82,6 +82,22 @@ fn thumb_short_data_mapping() {
     );
 }
 
+#[test]
+#[cfg(feature = "arm")]
+fn read_arm_v4bx() {
+    // R_ARM_V4BX relocations mark `bx` instructions so the linker can optionally
+    // rewrite them for ARMv4 interworking.
+    let diff_config = diff::DiffObjConfig::default();
+    let obj =
+        obj::read::parse(include_object!("data/arm/v4bx.o"), &diff_config, diff::DiffSide::Base)
+            .unwrap();
+    let symbol_idx = obj.symbols.iter().position(|s| s.name == "v4bx_func").unwrap();
+    let diff = diff::code::no_diff_code(&obj, symbol_idx, &diff_config).unwrap();
+    let output = common::display_diff(&obj, &diff, symbol_idx, &diff_config);
+    // The `bx lr` still disassembles normally; the V4BX hint is simply dropped.
+    assert!(output.contains("bx"), "expected a `bx` instruction, got:\n{output}");
+}
+
 #[test]
 #[cfg(feature = "arm")]
 fn trim_trailing_hword() {
diff --git a/objdiff-core/tests/data/arm/v4bx.o b/objdiff-core/tests/data/arm/v4bx.o
new file mode 100644
index 0000000000000000000000000000000000000000..11271151f520fc08a9ef2d22990ce6033066da30
GIT binary patch
literal 644
zcmah_yH3ME5S)u~up3?-4?zQxC8UGG1!Yn|1r17%&R|3&K*+wJQ1Nqo0woP!0<-v5
zzR+Z?)z0kA&aLnL{PMyW0}X=$Jp=YSl9qph0y#45|D1e}x7l#DtEMpPglRd!aFCfi
z9#+$+CJXLB!Y_^lEB_RWh6z$C`q&cnp~Gug&2R2!&$r>IkZRkvC+{j&-*ojsQByx!
zU(Y@4o%0U1YFpUx^_6wrH`8k7>$bmS2|D1pY&i@%d8>Fw#k=h1%n?)KlbJDPPUb}?
z{3vjJnKSY@^hJ)@6#X*YX{UKn5AoYk!m55!2T^}QEJLeI*-`e}V9Gz}orL&ct_cXC
Qew*a6?u&dBG*VRe3+HPmU;qFB

literal 0
HcmV?d00001